JPH0191394A - Read only memory - Google Patents

Abstract

PURPOSE:To optimize a precharge time and a discharge time by generating a control signal for a ROM from the state of an output line that discharges a potential set by precharging in another potential at every reading. CONSTITUTION:At the timing of the rise of a read signal, a signal phiAS comes in L, the P-MOS of a word line precharge PCh circuit 102 turns on, and all the word lines are made PCh. A signal phiMS also comes in L simultaneously, the P-MOS of a memory data output line charge circuit 101 also turns on, and output lines are made PCh. Accordingly, an EN signal comes in an H-level, and a control circuit 107 makes the phiAS in H to release the PCh state of the word lines. One piece of word line selected by an address recorder 103 is connected to a GND electrode, and its charges are discharged, and it comes in L. The circuit 107 shifts the phiMS to H at the timing of rising of the EN signal to turn off the P-MOS of the circuit 102. A discharge sensing circuit 109 makes a WAIT signal in L upon completion of a discharge to inform the fulfilment of a ROM output.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to memory circuits, and in particular to read-only memories (Re
AdOnly Memory (hereinafter referred to as ROM) output control.

Conventional technology This ROM will be explained below with reference to the drawings.

Figure 4 shows 8 x 4 bits (3 addresses, 4 bits)
It is an ion implantation switching type N-channel type MO3FET vertically stacked ROM (output). The illustrated ROM includes an address decoder 403 that decodes an address signal to read data stored in a storage data section 404;
A word line precharge circuit 402 that precharges the word line when reading data stored in the storage data section 404, an output line charge circuit 401 that charges the data output line, and a latch circuit that latches the output data. 405.

FIG. 5 is a time chart of control signals for the ROM shown in FIG. 4. According to FIG. 5, such ROM is SO
One operation is completed in 5 states of ~S4. First, the address sampling signal φAS becomes low level at the timing of SO, and the P-channel type MOS FET (hereinafter referred to as P-MOS) of the word line precharge circuit 402
is in the on state, and all word lines are at high level (Van
is charged to potential〉. In other words, the word line is in a precharge state.

At the same time, the memory sampling signal φMS also becomes low level, turning on the P-MOS of the storage data output line charge circuit 401. Here, the storage data section 4
04 N-channel type MO3FET (hereinafter referred to as N-MOS
Since the gate is a word line, all output lines are on, and all output lines are at high level (Von potential).
is charged. In other words, the output line is in a precharge state.

During the 81 period, the above-mentioned precharge state continues, and the data line and output line are each in the charged state. At the timing of S2, the address sampling signal φAS becomes high level, the precharge state of the word line is released, and only one word line selected by the address decoder 403 is connected to the GND electrode during the precharge period. The charged charges are discharged and become low level. On the other hand, other unselected word lines are not connected to any electrode and hold charged charges.

In contrast, the output line is still in a precharged state. This is because the output line has a larger parasitic capacitance than the word line, so the precharge period is usually longer.

In the 83rd period, the memory sampling signal φi also becomes high level, and the storage data output line charge circuit 402
The P-MOS is turned off, the N-MOS is turned on in its place, and all output lines are connected to the GND electrode. Here, N of the storage data section 404 gates the selected word line mentioned above.
-If the MOS is an enhancement type FET, its N
-MOS is turned off and the potential of the output line is not transmitted to the output terminal. Also, if it is a depletion type FET, its N-F
ET transmits the potential of the output line to the output terminal without being affected by the gate potential. Therefore, N− of the storage data section 404
By setting the FET to enhancement type or depletion type by switching the ion implantation, the potential of the output line is held (high level "1") or the charge is removed to the GND electrode and the GND potential is set (low level). “0”) can be controlled. The output logical value is latched in the latch 405 at the timing of S4, and the RO
Used as output data of M.

Problems to be Solved by the Invention As is clear from FIG. 5, in the conventional ROM described above, the time required to precharge the word line or output line, and the time from when data is output to the output line until the data is latched. Each time depends on the clock frequency. Therefore, if it is desired to operate the ROM faster or slower than usual, this can be done by changing the tarok frequency.

However, in this case, there is a problem that if the ROM is operated faster or slower than its capacity, the ROM will output incorrectly.

For example, if the precharge time becomes shorter than allowable when the clock frequency is increased, the sampling period will begin before the battery is completely charged, making it impossible to output a high level correctly. On the other hand, if the discharge time is shorter than allowable, the battery will be latched before being completely discharged, making it impossible to output a low level correctly.

In addition, if the clock frequency is lowered and the time from when data is output to the output line to when the data is latched becomes longer than allowable, the potential of the output line that is held at a high level will gradually decrease and the logic If the threshold value is exceeded, the high level will not be output correctly.

Moreover, the capacity limit of the ROM depends on various parameters of the device manufacturing process, and therefore varies from manufacturing plant to manufacturing plant, loft to loft, and device to device, and cannot be generally determined.

Therefore, the present invention solves the above-mentioned problems, and
It is an object of the present invention to provide a read-only memory that can always obtain accurate output data even when the clock frequency is increased or decreased.

Means for Solving the Problems According to the present invention, the word line and storage data output line are precharged, and the potential of the output line set by the precharge function is maintained or set to another potential. A ROM having a control function for outputting stored data from the stored data output line by controlling whether to discharge the data, and an output for discharging to a different potential each time the potential set by the precharge function is read. A line is provided separately from the storage data output line, and the state of the output line is used as a ROM control signal to optimize the precharge time and discharge time.

According to the ROM according to the present invention described above, the precharge time and the discharge time are independent of the clock frequency.

Therefore, even if the clock frequency is changed, precharging and discharging can be performed perfectly.
It becomes possible to obtain accurate ROM output.

In addition, the present invention has the advantage that it can be easily implemented by simply adding an output line for one bit to a conventional ROM.

Example Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, and as in FIG.
4bit (8 address, 4bit output) N-MO3
It is a vertically stacked ROM and is an ion implantation switching type. R shown in the diagram
OM includes an address decoder 103 that decodes an address signal to read data stored in the storage data section 104, and a word decoder 103 that precharges a word line when reading data stored in the storage data section 104. It includes a line precharge circuit 102, an output line charge circuit that charges the data output line, and a latch circuit 105 that latches the output data. This configuration is similar to the ROM shown in FIG. 4. However, the output line (
(for sense) 106 is connected, and its output line (for sense)
106 is connected to a precharge sense circuit 108 and a discharge sense circuit 109 via a delay circuit 11O. The output of the precharge sense circuit 108 is input to the precharge/discharge control circuit 107, and the READ signal is also input to the precharge/discharge control circuit 107, and the address sampling signal φA5 and the memory sampling signal φ, . Output. Furthermore, the output of the discharge sense circuit 109 is
It is input to the latch circuit 105 as a latch signal, and
It is also output as a WAIT signal.

The element with the symbol 111 is a depletion type N-channel MO3FET, and the element with the reference number 111 is a depletion type N-channel MO3FET.
The element designated by 12 is an enhancement type P-channel MO3FET.

FIG. 2 is a time chart of control signals of the ROM shown in FIG.

In the ROM of the illustrated embodiment, the address sampling signal φAs becomes low level at the rising timing of the READ signal, and the word line precharge circuit 102 P-M
The OS is turned on and all word lines are charged to high level. That is, the word line is in a precharged state. At the same time, the memory sampling signal φ□ also becomes low level, and the P of the storage data output line charge circuit 101
- Turn on the MOS. Here, the storage data section 10
Since the N-MOS No. 4 and the N-MOS belonging to the output line 106 have the word line as their gate, they are all turned on, and all output lines including the output line 106 are charged to a high level. In other words, the output line is in a precharge state.

This output line precharge state can be known from the EN signal of the precharge sense circuit 108. When precharging is completed, the EN signal becomes high level. After confirming that the EN signal has become high level,
The precharge/discharge control circuit 107 sets the address sampling signal φ6 to a high level, and the precharged state of the word line is released. Therefore, only one word line selected by address decoder 103 is connected to GND.
The charge connected to the electrode and charged during the precharge period is discharged and becomes a low level. The word line of the unselected cell is not connected to any electrode and holds a charged charge.

Furthermore, the precharge/discharge control circuit 107 sets the memory sampling signal φMS to a high level at the timing of the rise of the EN signal, and the output line charge circuit 1
Turn off the P-MOS of 02.

Furthermore, the NMOS is turned on and all output lines are connected to the G'ND electrode. At this time, if the N-MOS of the storage data section 104 that gates the selected word line is an enhancement type FET, the N-MOS is turned off and the output line does not transmit the potential to the output terminal, but goes high. Outputs level (holding potential). Further, in the case of a depletion type FET, the N-MOS remains on because it is not affected by the gate potential, and therefore transmits the potential to the output terminal and outputs a low level. Since all N-MOS belonging to the output line 106 are depletion type FETs, no matter which word line is selected, the output line is connected to the GND electrode and outputs a low level "0".

Therefore, the discharge state can be known from the output line 106. The discharge sense circuit 109 sets the WAIT signal to a low level when the discharge is completed, and transmits to the outside that the ROM output has been determined.

The output data is latched at the falling timing of the WAIT signal and becomes output data of the ROM.

Note that the discharge capacity and precharge capacity of the output line 106 must be the lowest among all output lines. Therefore, in this embodiment, an enhancement type FE is connected to the output line 106.
This is done by adding a delay circuit 110 corresponding to the difference in performance between T and depletion type FET.

As described above, the ROM according to the present embodiment includes the output line 106 which outputs a low level after always discharging the potential of the precharged output line.
By sensing 06, even if the clock frequency is changed, precharging and discharging can be performed completely and accurate ROM output can be obtained. In other words, even if the clock frequency is increased, the precharge sense circuit 1
08 senses the precharge state and does not set the EN signal to high level until it is completely charged.

When the EN signal becomes high level, it is a discharge period, and no extra precharge time is required. Furthermore, the discharge state is also sensed by the discharge sense circuit 109, and the WAIT signal is not set to low level until the discharge is reliably performed, so that data will not be output when the discharge cine is sufficient.

In addition, when the clock frequency is slow, as shown in the time chart of FIG. 3, the data on the output line is latched when the WAIT signal of the discharge sense circuit falls, that is, when the output line 106 becomes low level. . Therefore, the precharged potential can be held until the 84th period.

Effects of the Invention Accordingly, as is clear from the above description, according to the present invention, since precharging and discharging can be performed completely, highly reliable ROM output can be expected to be obtained. In addition, especially at high frequencies, there are many wait states, so although the actual operating frequency drops, it is possible to operate without restrictions at low frequencies, and ROM
can significantly expand the operating frequency range. Furthermore, precharging and discharging can be performed in the minimum amount of time required for the device, which is highly efficient and economically effective.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of a read-only memory according to the present invention, and FIGS. 2 and 3 are time charts of control signals of the ROM shown in FIG. 4 is a diagram showing an example of a conventional ROM, and FIG. 5 is a diagram showing an example of a conventional ROM shown in FIG.
3 is a time chart of control signals of M. (Main reference numbers) 101, 401... Output line charge circuit 102, 402
...Word line precharge circuit 103, 403...Address decoder 104, 404...Stored data section 105, 405...Latch circuit 106...Output line (for sense) 107...Precharge/discharge control circuit 108... Precharge sense circuit 109...
Discharge sense circuit 110...Delay circuit 112...Enhancement type P-channel MO3FET

Claims (1)

[Claims] A precharging function for word lines and storage data output lines;
A read-only memory comprising a control function that outputs stored data from the stored data output line by controlling whether to hold the potential of the output line set by the precharge function or discharge it to a different potential. An output line that discharges to a different potential each time the potential set by the precharge function is read is provided separately from the storage data output line, and the precharge time is determined by detecting the state of the output line. and read-only memory characterized by optimizing discharge time.