JPH0192846A - Testing system for peripheral device - Google Patents

Abstract

PURPOSE:To attain a highly efficient operation test by allowing a state deciding means to decide the operation test of a peripheral device at the time of accessing the peripheral device in the operation test and sending information indicating the execution of the operation test to an accessing source. CONSTITUTION:When an access instruction 123 for accessing the peripheral device 131 is inputted to the state deciding means 121, the means 121 decides that peripheral device 131 is in an operation test in accordance with state information set up in a state information setting means 111 and sends information 125 indicating the execution of the test to the accessing source. At the time of accessing the peripheral device 131 in the operation test, and the peripheral device 131 in the operation test is decided by the means 121 and the information 125 indicating the execution of the test is sent to the accessing source. Thus, the operation test can be efficiently executed.

Description

[Detailed Description of the Invention] [Summary] Regarding a peripheral device test method when performing an operation test of a peripheral device shared by a plurality of logical devices, the purpose of this invention is to efficiently perform an operation test, and to start an operation test. test status indicating means for outputting a start instruction corresponding to the operation test and an end instruction corresponding to the end of the operation test; At the same time, when a termination instruction is introduced, the state information setting means cancels the set state information, and when an access instruction for accessing a peripheral device is introduced, the state information setting means sets the state information. and status determination means for determining whether the peripheral device is under an operation test according to the status information received, and sending information indicating that the peripheral device is under test to the access source of the peripheral device, In some cases, the access source is configured to send information indicating that the test is in progress.

[Industrial application field]

The present invention relates to a peripheral device testing method, and more particularly to a peripheral device testing method for testing the operation of a peripheral device shared by a plurality of logical devices.

[Conventional technology]

In a computer system that includes multiple logical devices (eg, host computers), the multiple host computers may share peripheral devices. An example of a shared peripheral device is a mass storage device (Mass storage device).
storage system (hereinafter referred to as MSS).

When a host computer is accessing the MSS, if another host computer tries to access the same area (same cartridge) of the MSS, it will receive a notification that the access is in progress and will wait until the access is completed.

[Problem that the invention seeks to solve]

By the way, in the above-mentioned system, when performing an operation test of a shared MSS after recovering from a failure that occurred in the MSS, there is an inconvenience if the MSS is accessed for a long time for the operation test. Ta.

For example, when another host computer accesses the area of the Mss under operation test, the access state continues for more than a predetermined period of time, resulting in an erroneous determination that a failure has occurred.

In order to avoid such inconveniences, conventional methods have been to stop the operation of host computers other than the host computer under test, or to shut down the MSS under test and other hosts by instructions from the host computer under test. Operation tests were conducted by disconnecting the computer.

Therefore, since the host computer that is conducting the operational test needs to restrict access from other host computers, there is a problem in that it takes time and effort to conduct the operational test, and the efficiency of the operational test is low.

The present invention was created in view of the above points, and an object of the present invention is to provide a peripheral device testing method that enables efficient operation testing.

[Means for solving problems]

FIG. 1 is a principle block diagram of a peripheral device testing method according to the present invention.

In the figure, a test status instructing means 101 in a peripheral device test method when performing an operation test of a peripheral device 131 shared by a plurality of logical devices includes a start instruction 113 corresponding to the start of the operation test, and an end instruction 113 corresponding to the start of the operation test. The end instruction 115 corresponding to the end instruction 115 is output.

The state information setting means 111 sets state information indicating that an operation test is being performed when a start instruction 113 is introduced, and also sets the set state information when an end instruction 115 is introduced. Delete the information.

The state determining means 121 determines that the peripheral device 131 is undergoing an operation test according to the state information set in the state information setting means 111 when an access instruction 123 for accessing the peripheral device 131 is introduced. and sends information 125 indicating that the test is in progress to the access source of the peripheral device 131.

Therefore, as a whole, when the peripheral device 131 that is undergoing an operation test is accessed, the information 12 indicating that the test is being performed is sent to the access source.
5.

[For production]

The test status instructing means 101 transmits the start instruction 113 to the state determining means 12 in response to the start of the operation test of the peripheral device 131.
Supply to 1. The state determining means 121 determines whether the start instruction 11
3, the peripheral device 131 sets status information indicating that an operation test is being performed.

Further, the test status instructing means 101 supplies a termination instruction 115 to the state determining means 121 in response to the end of the operation test of the peripheral device 131. The state determining means 121 receives the termination instruction 115 and cancels the set state information.

Access instruction 12 for accessing peripheral device 131
3 is introduced into the state determining means 121, the state determining means 121 determines that the peripheral device 131 is undergoing an operation test according to the state information set in the state information setting means 111, and performs the test. Information 125 representing the contents is sent to the access source.

In the present invention, when the peripheral device 131 that is undergoing an operation test is accessed, the status determining means 121 determines that the peripheral device 131 is undergoing an operation test, and sends information 125 indicating that the test is being performed to the access source. , it is possible to perform operation tests efficiently.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 2 shows the configuration of an embodiment to which the peripheral device testing method of the present invention is applied.

Here, the correspondence between the embodiment of the present invention and FIG. 1 will be shown.

The test status instruction means 101 is a host computer 201
corresponds to

The status information setting means 111 corresponds to the main control unit 210° test status register 211.

The start instruction 113 corresponds to a test state setting command supplied from the host computer 201 to the controller 200.

The termination instruction 115 corresponds to a test state cancellation command supplied from the host computer 201 to the controller 200.

The state determining means 121 corresponds to the main control section 210.

The access instruction 123 corresponds to the access instruction of the MSS 231 supplied from the host computer 203 to the controller 200.

The information 125 indicating that a test is in progress corresponds to a notification sent from the main control unit 210 to the host computer 203 to the effect that an operation test is in progress.

The peripheral device 131 corresponds to the MSS 231.

Examples of the present invention will be described below assuming that the correspondence relationship as described above exists.

In FIG. 2, the computer system according to the embodiment of the present invention has four host computers 201, 203, 205, 2 that perform data processing in the system.
07, two MSSs 231 and 233 for storing data processed by these host computers,
It includes an optical disk device 235 and a controller 200 that controls data input/output to the MS3231.233 and the optical disk device 235.

The controller 200 has four host computers 20
1,203,205,207.2 MSS231,2
33 and an optical disk device 235.

In addition, the four host computers are connected to the controller 20
0, MSS231, 233. Optical disk device 2
Any of the 35 devices can be accessed.

Furthermore, the controller 200 includes a main control unit 210 that controls the entire controller 200, and peripheral devices (MSS 231, 23) shared by the four host computers.
3. A test status register 211 that stores information indicating that the optical disk device 235) is undergoing an operation test, a port 241 for outputting data between the host computer 201, and the host computer 203. A boat 243 for inputting and outputting data, a boat 245 for inputting and outputting data to and from the host computer 205, and a boat 247 for inputting and outputting data to and from the host computer 207. We are prepared.

In this embodiment, the control operation during the operation test (operation of notifying the host computer that the operation test is in progress)
Focus on.

1-Saku Niwa Saramiki Next, the operation of the peripheral device testing method according to the embodiment of the present invention described above will be explained.

Based on instructions from the host computer 201, the MSS
The operation test shall be carried out at 231, and furthermore, the
During the SS231 operation test, the host computer 203
Consider the case where an access instruction for the MSS 231 is output from the MSS 231.

First, the host computer 201 sends a test state setting command to the controller 200 before starting an operation test of the MSS 231. The main control unit 210 controls the boat 24
1, the test status register 21
Information indicating that the MSS 231 is conducting an operation test is stored in the area corresponding to the No. 1 MSS 231.

For example, if the test status register 211 is MSS231.23
3. It is assumed that each optical disk device 235 has a capacity of 3 bits corresponding to 1 bit data, and the bit corresponding to the device under operation test is set to "1°" during normal operation (or when no operation instruction is given). Set the bit corresponding to the device (not available and on standby) to "θpa". Therefore, the main control section 21
0 is set in M33 of the test status register 211 in response to the test status setting command received from the host computer 201.
"1" is stored in the first bit corresponding to 231.

After that, the host computer 201 starts an operation test of the MSS 231.

Next, consider a case where the host computer 203 accesses the MSS 231 while the MSS 231 is undergoing an operation test.

From the host computer 203 to the controller 200,
When an instruction to access MSS 231 is introduced, main control unit 210 reads bit data of test status register 211 corresponding to MSS 231 accessed from host computer 203 . Main control section 21
0 is determined by reading the first bit of the test status register 211 and finding that the first bit is "1".
31 is under operation test.

Next, the main control unit 210 notifies the host computer 203 via the boat 243 that the MSS 231 is undergoing an operation test. Upon receiving the notification, the host computer 203 notifies the operator that the MSS 231 is undergoing an operation test, or displays peripheral devices other than the MS3231 (or areas other than the M33231 where the operation test is being conducted).
The MSS 231 outputs an access instruction, or waits until the operation test of the MSS 231 is completed.

When the operation test of the MSS 231 is completed, the host computer 201 sends a test state release command to the controller 200. When the main control unit 210 receives the instruction via the port 241, it cancels the data "1" stored in the first bit of the test status register 211 and changes it to "0".

Next, during the operation test of the MSS 231, the main control unit 210 sends a notification of the end of the operation test to the host computer 203 that sent the notification to the effect that the operation test is in progress.

Thereafter, the first bit of the test status register 211 is “O11”.
Therefore, the main control unit 210 controls the MSS 23 from the four host computers 201, 203, 205, and 207.
1 access, data input/output operations can be performed.

■Summary of the above In this way, the host computer 201
A test state setting command corresponding to the start of operation test No. 1 is sent to the controller 200. When the main control unit 210 receives the test state setting command from the host computer 201, it rewrites the first bit of the test state register 211 to "1 pass".
From 07 onwards, MSS231 access instructions are sent to controller 2.
00, the main control unit 210 detects that the first bit of the test status register 211 is “1”,
It recognizes that the MSS 231 is undergoing an operation test, and sends back a notification to the effect that the MSS 231 is undergoing an operation test to the accessing host computer. Moreover, when the operation test of MSS231 is completed, the host computer 201
A test state release command corresponding to the completion of the operation test No. 31 is sent to the controller 200. When the main control unit 210 receives the test state release command from the host computer 201,
The first bit of the test status register 211 is changed to "0".

Therefore, if any host computer sends an access instruction to the MSS 231 to the controller 200 while the MSS 231 is undergoing an operation test, the controller 200 will send the MSS 2
By having the computer receive a notification that 31 is undergoing an operation test, the operation test can be carried out efficiently.

In particular, the burden on the operator of the host computer who conducts the operation test is lightened because there is no need to consider access from other host computers. Furthermore, by eliminating manual operations by the operator, it is possible to eliminate the effects of erroneous operations on normal processing.

Note that in the embodiment of the present invention described above, the host computer was considered as a logical device, but each CPU in a multi-CPU system (including the memory that the CPU directly processes) The present invention can also be applied when configuring a system by considering it as a logical device.

In addition, in the embodiment, MSS231.23 is used as a peripheral device.
3. Although the optical disk device 235 was considered, any peripheral device that can be shared (for example, a hard disk device) may be used.

Furthermore, in ``correspondence between examples and FIG. 1'',
Although the correspondence between the present invention and the embodiments has been described, those skilled in the art will easily assume that the present invention is not limited to this and that there are various modifications.

〔Effect of the invention〕

As described above, according to the present invention, when a peripheral device that is undergoing an operation test is accessed, the state determining means determines that the peripheral device is undergoing an operation test, and sends information indicating that the test is being performed to the access source. , you can perform operation tests efficiently.
It is extremely useful in practical terms.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the principle of the peripheral device testing method of the present invention, and FIG. 2 is a block diagram of an embodiment to which the peripheral device testing method of the present invention is applied. In the figure, 111 is a status information setting means, 113 is a start instruction, 115 is an end instruction, 121 is a status determination means, 123 is an access instruction, 125 is information indicating that the test is in progress, 131 is a peripheral device, 200 is a controller, 201. 203, 205, and 207 are host computers, 210 is a main control unit, 211 is a test status register, and 231, 233 is an MSS. 235 is an optical disk device, and 241, 243, 245, and 247 are boats. The present invention θR Tamarifu *Q,,,ri■ Figure 1 Example of helmet q Composition diagram

Claims (1)

[Claims] Peripheral device (131) shared by multiple logical devices
In a peripheral device testing method when performing an operation test, a test status indicating means (101) outputs a start instruction (113) corresponding to the start of the operation test and an end instruction (115) corresponding to the end of the operation test. ) and the start instruction (113
) is introduced, status information indicating that an operation test is being conducted is set, and the termination instruction (1
15) is introduced, and a state information setting means (111) for canceling the set state information and an access instruction (123) for accessing the peripheral device (131) are introduced. Then, it is determined that the peripheral device (131) is undergoing an operation test according to the status information set in the status information setting means (111), and a message indicating that the peripheral device (131) is being accessed is informed that the test is being performed. a state determining means (121) that sends information (125) representing the status, and when the peripheral device (131) undergoing an operation test is accessed, the information (125) representing the status is transmitted to the access source;
25) A testing method for a peripheral device, characterized in that the peripheral device is configured to transmit data.