JPH0194706A - Sc type off-set compensating circuit - Google Patents

Abstract

PURPOSE:To obtain a compensating circuit which has a small off-set compensating error and is suitable for an MOS integrated circuit by generating a compensating signal equal to the absolute value in a positive direction and a negative direction with a switched capacitor integrator. CONSTITUTION:According to the fact whether the output of an amplifier circuit 2 is larger or smaller than a reference voltage, the output of a comparator circuit 4 becomes H or L. When an output is H, a counter 8 and a monostable multivibrator 10 are operated, and after pulses phi1 and phi2 occur, pulses phi3 and phi4 are generated. Thus, switches S1 and S2 of an SC integrator 6 are closed for a constant time, next, switches S3 and S4 are closed for a fixed time and therefore, the integrator 6 becomes an inversion integrating action and generates a negative compensating signal. Next, when the output is made smaller than the reference voltage, the output of the circuit 4 becomes an L, after pulses phi1 and phi3 are generated, pulses phi2 and phi3 occur, the integrator 6 executes the non-inverting integrating action and generates a positive compensating signal. Since the positive negative compensating signals are determined by the ratio of C1 and CS, the absolute value is equal and the error of the off-setting does not occur.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an SC type offset compensation circuit, and particularly to an MO8 offset compensation circuit.
This invention relates to an integrated circuit SC type offset compensation circuit.

[Conventional technology]

Conventionally, this type of offset compensation circuit uses a charging/discharging circuit to form an offset compensation signal for an input signal.

FIG. 4 is an offset compensation circuit diagram for explaining a conventional example.

As shown in FIG. 4, this compensation circuit includes an amplifier circuit 2 connected to an input terminal 1, which amplifies a predetermined input signal and outputs it as an output signal, and an amplifier circuit 2, which is connected to an input terminal 1, and an amplifier circuit 2, which is connected to one input terminal, and an amplifier circuit 2, which is connected to an input terminal 1 and amplifies a predetermined input signal to produce an output signal. An input analog adder 3 and a comparison circuit 4 that compares the output voltage of the two-input analog adder 3 with a reference voltage Vr3.
, the overflow signal that occurs when counting is performed with the output of the comparator circuit 4 at a high level (hereinafter referred to as "H") or a low level (
A control signal generating circuit 5' generates a control pulse φb or φ in response to whichever of the overflow signals occurs when counting is performed in the state of "L" (hereinafter referred to as "L"), and the control pulse φ1. Switches S, , S each controlled by φb
a charging/discharging circuit 15 for charging or discharging an integral capacitor C with a predetermined current by closing b, and a compensation signal line that applies the voltage across the integral capacitor C to the other input terminal of the two-input analog adder 3; 7.

In this compensation circuit, the output signal of the comparator circuit 4 is applied to one input terminal of the AND circuit A1 of the control signal generation circuit 5', and is applied to the other input terminal of the AND circuit A1 of the control signal generation circuit 5'.
. is input and the logical product is taken, and the output of the AND circuit AI is sent to the up input terminal U of the n-bit up counter 8.
1 is input. Further, the output signal of the comparison circuit 4 is
It is inverted by the inverter 11 of the control signal generation circuit 5' and the AN
A clock pulse φ is applied to one input terminal of the D circuit A2, and a clock pulse φ is applied to the other input terminal. are input, a logical product is taken, and the output thereof is input to the up input terminal U2 of the n-bit up counter 9. Here, if the output of the comparison circuit 4 is "H", the clock pulse φ. is counted by the n-bit up counter 8, and when it is counted 2'' times, the overflow signal C1 becomes "H" and the monostable multivibrator
10 is output. This output signal is differentiated by a monostable multivibrator 10 to generate a control pulse φb. This control pulse φb is applied to the switch S of the charging/discharging circuit 15.
b is closed to discharge the integral capacitor C with a constant current, and the voltage of the integral capacitor C is applied to the two-input analog adder 3 as a correction signal for the input signal via the amplifier circuit 16 with a gain of 1 and the compensation signal line 7. Conversely, if the output of the comparison circuit 4 is "L", the clock pulse φ. is counted by the n-bit up counter 9, and when the 2" figure is counted, the overflow signal C2 becomes "H" and the monostable multivibrator-1
1 is output. This output signal is differentiated by a monostable multivibrator 11 to generate a control pulse φ.

This control pulse φ1 closes the switch S1 of the charge/discharge circuit 15 to charge the integral capacitor C with a constant current, and the voltage is sent to the two-input analog adder 3 via the amplifier circuit 16 and the compensation signal line 7 to correct the input signal. Add as a signal. In this way, an output signal in which the DC component of the input signal is corrected to the reference voltage vr3 is obtained from the output side of the two-input analog adder 3.

[Problem that the invention seeks to solve]

However, this offset compensation circuit has a charging/discharging circuit 15GgpMOS transistor T r l + T r
2 and nMOs) transistor Tr3. There is an offset compensation error due to the use of a current mirror circuit consisting of T,4. That is, when the switch SS is closed, the current I ma flowing through the pMOS transistor Tr2
When the switch Sb is closed, the nMOS transistor Tr
The current Isb flowing through the current Isb is not necessarily equal to the current Isb flowing through the current Isb. It is the drain of pMOS transistor Trl and nMO3
) Potential V at the connection point of the train of transistor Tr3 and pMO8) Drain of transistor Tr2 and nMO8)
This is because the potential (2) at the connection point of the transistor train is not necessarily equal to the potential (2). Therefore, the amount of change in the voltage of the integral capacitor C is 1■ during charging. '1, discharge time is l
If V, -1, then 1■. ``1≠lV, -1.

On the other hand, if the time when the input signal of the comparator circuit 4 is higher than the reference voltage Vr3 is t+, and the time when it is lower is t-, then the number of times charging and discharging are performed is proportional to t- and t+, respectively. The equilibrium condition of such an offset compensation circuit is t+,1
y, -l = t-・l Vc"1. But &4
, as mentioned above, the amount of change in the voltage of the integrating capacitor C is l
If V," l≠I V, -1, t+≠t-, which generates an offset compensation error.

Since the conventional offset compensation circuit described above uses a current mirror circuit, it has the disadvantage that the offset compensation error becomes large as a result of the difference in magnitude between the positive direction compensation voltage and the negative direction compensation voltage.

An object of the present invention is to provide an SC type offset compensation circuit that has a small offset compensation error and is suitable for MO3 integrated circuit implementation.

[Means for solving problems]

The SC type offset compensation circuit of the present invention includes a two-input analog adder that adds an input signal and a compensation signal, and a two-input analog adder that is connected to the front or rear stage of the two-input analog adder to amplify the input signal and an amplification circuit that adds the output to an analog adder or amplifies the output of the two-input analog adder to provide an output signal, and compares the output of the two-input analog adder or the output of the amplification circuit with a first reference voltage; and an overflow signal that occurs when the output of the comparison circuit is counted in a high level state, or an overflow signal that occurs when it is counted in a low level state, whichever comes first. and means for simultaneously generating the third and fourth pulses after simultaneously generating the second pulse, and means for simultaneously generating the second and fourth pulses after simultaneously generating the first and third pulses. a control signal generation circuit having an operational amplifier, an integrating capacitor,
a sampling capacitor and said sampling capacitor;
a first switch connected between one terminal of the capacitor and a ground terminal and controlled by the first pulse of the control signal generating circuit; a first switch connected between the other terminal of the sampling capacitor and the installation terminal; a second switch controlled by a pulse; a third switch connected between the other terminal of the sampling capacitor and a second reference voltage terminal and controlled by the third pulse; an inverting input terminal of the operational amplifier; and a fourth switch connected between one terminal of the sampling capacitor and controlled by the fourth pulse, and an overflow signal generated when counting is performed with the output of the comparator circuit at a high level. a switched capacitor (SC) integrator that performs an inverting integration operation or a non-inverting integration operation in response to whichever precedes an overflow signal that occurs when counting in a low level state;
The output of the integrator is configured to be applied as the compensation signal to the two-input analog adder.

〔Example〕 .

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is an SC type offset compensation circuit diagram for explaining a first embodiment of the present invention.

As shown in FIG. 1, in the offset compensation circuit of this embodiment, an amplifier circuit 2 is connected to an input terminal 1 and amplifies a predetermined input signal, and an output terminal of this amplifier circuit 2 is connected to one input terminal. A two-input analog adder 3, a comparison circuit 4 that compares the signal voltage at the output terminal of the two-input analog adder 3 with a first reference voltage Vrl, and a comparator circuit 4 connected to the other input terminal of the two-input analog adder 3. The provision of the compensation signal line 7 is the same as in the conventional example shown in FIG. , the first and second pulses φ1. OR circuit 0 for φ2
1. ．． 02, the third and fourth pulses φ and 2φ4 are generated simultaneously by the OR circuit 03.04, or the first and third pulses φ1゜φS are generated simultaneously, and then the second and fourth pulses φ and 2φ4 are generated simultaneously by the OR circuit 03.04. Four pulses φ2. φ4
A control signal generation circuit 5 is provided that simultaneously generates the
A switched capacitor (SC) integrator 6 having four switches 81 to S4 controlled by the pulses φ1 to φ4, an operational amplifier circuit 14, and various capacitors is provided. That is, the SC integrator 6 is inserted between the operational amplifier 14, the integrating capacitor CI, the sampling capacitor CS, and the inverting input terminal of the operational amplifier 14 and one terminal of the sampling capacitor CS. controlled fourth switch S4
, a first switch S1 inserted between one terminal of the sampling capacitor Cs and the ground terminal and controlled by the first pulse φ1, and a second reference voltage terminal between the other terminal of the sampling capacitor Cs and a second reference voltage terminal. A third switch S3 is inserted between vr2 and controlled by the third pulse φ3, and a second switch S3 is inserted between the other terminal of the sampling capacitor Cs and the ground terminal (because it is not necessarily required). It has a second switch S2 controlled by the pulse φ2 and a reset switch SR. Also, this SC integrator 6
is an inverted integral operation or a non-integral operation depending on whichever comes first: an overflow signal that occurs when counting is performed when the output of the comparator circuit 4 is in the “H” state, or an overflow signal that occurs when the output is counted in the “L” state. The SC integrator 6 has a function of performing an inverting and integrating operation, and the output of the SC integrator 6 is applied to the other input terminal of the two-input analog adder 3 via the compensation signal line 7. Further, the specific configuration of the control signal generation circuit 5 includes an inverter E 1, AND circuits A I and A 2, n-bit up counters 8 and 9, and a monostable multivibrator.
10 and 11 are the same as the conventional example, but the first pulse φ1 is a monostable multivibrator 10 and 11.
and the second pulse φ2 is given as the logical sum of the output of the monostable multivibrator 10 and the output of the monostable multivibrator 11 passed through the delay circuit 13. , and the third pulse φS is given as the logical sum of the output of the monostable multivibrator 11 and the output of the monostable multivibrator 10 passed through the delay circuit 12, and the fourth pulse φ4 is given as the Stable multivibrator-1
The difference from the conventional example is that the output of 0 is given as the logical sum of the output passed through the delay circuit 12 and the output of the monostable multivibrator 11 passed through the delay circuit 13.

Next, the operation of this offset compensation circuit will be described, taking n=3 as an example.

FIG. 2 is an operating signal waveform diagram of the compensation circuit in FIG. 1.

As shown in FIG. 2, when the output signal of the amplifier circuit 2 (offset voltage Vos in this case) is larger than the first reference voltage ■rl, the output of the comparator circuit 4 becomes "H", and if this state continues, the clock The n-bit up counter 8 counts by logical product with pulse φC. This counter 8
When it reaches 2" = 23 = 8, one pulse is output to the monostable altivibrator 10 due to overflow. In response, one pulse of a predetermined width differentiated from the monostable multivibrator 10 is generated. As a result, after the first and second pulses φ1 and φ2 are generated, the third and fourth pulses φ3 and φ4 are generated.
By closing the switches S, , S2 of the integrator 6 for a certain period of time, and then closing the switches S 3 + S 4 for a certain period of time, the SC integrator 6 performs an inverse integration operation, and a negative compensation signal ΔVC-= (Cs / C+) ・Generates vr2. Therefore, the output of the two-input analog adder 3 is also Δ
The above operation is repeated as long as the first reference voltage V is greater than 1. The output signal is Vr! When it becomes smaller, the output of the comparator circuit 4 becomes "L". If this state continues, it is inverted by the inverter 1 and becomes "H", and the n-bit up counter 9 counts by AND with the clock pulse φC, and 2" = 2
When 3 = 8 is reached, one pulse is output to the monostable multi-bi break-11 due to overflow. In response, one pulse of a predetermined width is generated from the monostable multivibrator 11, and the first and third pulses φ1. After φ3 occurs, the second and fourth pulses φ2. φ4 occurs. Therefore, the SC integrator 6 performs a non-inverting integration operation and generates a positive compensation signal Δvc''=Δ(Cs/C+)·■r2.Thereby, the output of the two-input analog adder 3 is changed to Δ■
Move it to the C+take positive side. That is, the positive compensation signal Δ
vC+ and the negative compensation signal Δ■C- are C! Since it is determined by the ratio of and Cs, IΔVC-1=IΔvc-1, and the offset error that conventionally occurs does not occur.

Furthermore, since it is obvious that this SC integrator 6 can be easily realized with an MO3 integrated circuit, it goes without saying that this embodiment is suitable for an MO8 integrated circuit.

FIG. 3 is a compensation circuit diagram similar to FIG. 1 for explaining a second embodiment of the present invention.

As shown in FIG. 3, in this second embodiment, a two-input analog adder 3 is connected immediately after the input terminal 1, and the output of the two-input analog adder 3 is used as the input of the amplifier circuit 2. 2 is used as an input signal of a comparator circuit 4 which compares the output of the second reference voltage with a first reference voltage. The circuit configuration and operating principle of this second embodiment are the same as those of the first embodiment described above, so a description thereof will be omitted. Note that, in terms of S/N characteristics, it is better to place the amplifier circuit in the front stage of the two-input analog adder 3 as in the first embodiment rather than in the latter stage of the two-input analog adder 3 as in the second embodiment.

〔Effect of the invention〕

As explained above, the SC type offset compensation circuit of the present invention uses an SC integrator to generate compensation signals with equal absolute values in the positive direction and the negative direction, thereby reducing offset compensation errors and using an MO8 integrated circuit. This has the effect of easily realizing the

[Brief explanation of the drawing]

FIG. 1 is an SC type offset compensation circuit diagram for explaining one embodiment of the present invention, FIG. 2 is an operating signal waveform diagram of the compensation circuit in FIG. 1, and FIG. 3 is a second embodiment of the present invention. FIG. 4 is a compensation circuit diagram similar to FIG. 1 for explaining the above, and FIG. 4 is an offset compensation circuit diagram for explaining a conventional example. DESCRIPTION OF SYMBOLS 1... Input terminal, 2... Amplification circuit, 3... Two-input analog adder, 4... Comparison circuit, 5... Control signal generation circuit, 6... SC integrator, 7...・Compensation signal line,
8, 9...n bit up counter, 10.11.
... Monostable multivibrator-112, 13... Delay circuit, 14... Amplifier circuit, A1-A3... AND
Circuit, ■1...Inverter, 02-04...OR
Circuits, 81 to S4...first to fourth switches, si.
...Reset switch, vrl...first reference voltage,
vr2...second reference voltage, φ1~φ4...first~
Fourth pulse, φC...clock pulse.

Claims (1)

[Claims] A two-input analog adder that adds an input signal and a compensation signal, and a two-input analog adder connected before or after the two-input analog adder to amplify the input signal and add it to the two-input analog adder or add the two-input analog adder. an amplifier circuit that amplifies the output of the analog adder to provide an output signal; a comparison circuit that compares the output of the two-input analog adder or the output of the amplifier circuit with a first reference voltage; and an output of the comparison circuit. After simultaneously generating the first and second pulses in response to the overflow signal that occurs when counting at a high level or the overflow signal that occurs when counting at a low level, whichever comes first. a control signal generation circuit having means for simultaneously generating third and fourth pulses and means for simultaneously generating second and fourth pulses after simultaneously generating the first and third pulses, an operational amplifier, an integrator; a first switch connected between one terminal of the sampling capacitor and a ground terminal and controlled by a first pulse of the control signal generating circuit, the other terminal of the sampling capacitor; a second switch connected between the installation terminals and controlled by the second pulse; a third switch connected between the other terminal of the sampling capacitor and the second reference voltage terminal and controlled by the third pulse; a fourth switch connected between the inverting input terminal of the operational amplifier and one terminal of the sampling capacitor and controlled by the fourth pulse, and the output of the comparator circuit is at a high level. Switched capacitor (SC) integration that performs inverting or non-inverting integration depending on whichever comes first: the overflow signal that occurs when counting at low level or the overflow signal that occurs when counting at low level. an SC type offset compensation circuit, characterized in that the output of the SC integrator is applied to the two-input analog adder as the compensation signal.