JPH0195759U - - Google Patents

Info

Publication number
JPH0195759U
JPH0195759U JP1987192375U JP19237587U JPH0195759U JP H0195759 U JPH0195759 U JP H0195759U JP 1987192375 U JP1987192375 U JP 1987192375U JP 19237587 U JP19237587 U JP 19237587U JP H0195759 U JPH0195759 U JP H0195759U
Authority
JP
Japan
Prior art keywords
outer frame
metal
lead
semiconductor chip
area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1987192375U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987192375U priority Critical patent/JPH0195759U/ja
Publication of JPH0195759U publication Critical patent/JPH0195759U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の実施例を示す断面図、第２図
は第１図の―断面図、第３図乃至第５図は従
来例を示す断面図及び平面図である。 １……リードフレーム、２……半導体チツプ、
３……インナーリード、４……外部リード、５…
…外枠、６……タイバー、７……金属箔、８……
絶縁フイルム、９……接続領域、１０……ワイヤ
ー。 FIG. 1 is a cross-sectional view showing an embodiment of the present invention, FIG. 2 is a cross-sectional view taken from FIG. 1, and FIGS. 3 to 5 are a cross-sectional view and a plan view showing a conventional example. 1...Lead frame, 2...Semiconductor chip,
3...Inner lead, 4...External lead, 5...
...Outer frame, 6...Tie bar, 7...Metal foil, 8...
Insulating film, 9... connection area, 10... wire.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] リードパターンを支持固定する金属製の外枠と
、前記外枠に連結支持されてこの外枠で囲まれた
領域内に延在され、且つその先端が前記領域内の
略中心部分を取り囲む様に配設された多数の金属
製リードパターンと、半導体チツプの大きさに対
応してその大きさが任意に設定され前記リードパ
ターン上に接着された矩形状の絶縁フイルムと、
前記フイルム上に貼着されボンデイング接続され
る接続領域を有する金属箔と、前記金属箔上に固
着された前記半導体チツプと前記リードパターン
の一端部とを接続するボンデイングワイヤとを具
備したことを特徴とする半導体装置。 a metal outer frame that supports and fixes the lead pattern; and a metal outer frame that is connected and supported by the outer frame and extends into an area surrounded by the outer frame, and whose tip surrounds a substantially central portion of the area. a large number of metal lead patterns disposed; a rectangular insulating film whose size is arbitrarily set according to the size of the semiconductor chip and which is adhered onto the lead patterns;
The present invention is characterized by comprising: a metal foil having a connection area stuck on the film and connected by bonding; and a bonding wire connecting the semiconductor chip fixed on the metal foil and one end of the lead pattern. semiconductor device.
JP1987192375U 1987-12-17 1987-12-17 Pending JPH0195759U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987192375U JPH0195759U (en) 1987-12-17 1987-12-17

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987192375U JPH0195759U (en) 1987-12-17 1987-12-17

Publications (1)

Publication Number Publication Date
JPH0195759U true JPH0195759U (en) 1989-06-26

Family

ID=31483237

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987192375U Pending JPH0195759U (en) 1987-12-17 1987-12-17

Country Status (1)

Country Link
JP (1) JPH0195759U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03169693A (en) * 1989-11-30 1991-07-23 Toshiba Corp Method for mounting electronic part

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5612360B2 (en) * 1976-06-21 1981-03-20
JPS58143541A (en) * 1982-02-22 1983-08-26 Hitachi Ltd Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5612360B2 (en) * 1976-06-21 1981-03-20
JPS58143541A (en) * 1982-02-22 1983-08-26 Hitachi Ltd Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03169693A (en) * 1989-11-30 1991-07-23 Toshiba Corp Method for mounting electronic part

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