JPH0197192A - Motor controller - Google Patents

Abstract

PURPOSE:To protect an entire control system safely, by blocking the gate of a thyristor upon occurrence of synchronization shift of an output signal from a synchronous signal output means and separating a motor from the output side of a thyristor converter. CONSTITUTION:A speed control circuit 2 outputs a current reference signal corresponding to a speed difference while a current control circuit 4 outputs a phase control reference signal 4a corresponding to a current difference. A power source synchronizing circuit 6 outputs a power source synchronization signal 6a from a voltage signal 5a. A phase control circuit 7 outputs a firing signal 7a for a thyristor inverter 8 based on the phase control reference signal 4a and the power source synchronization signal 6a. A power source synchronization detecting circuit 17 detects shift of synchronization from the phase of phase voltage of an AC power source bus 12 based on the voltage signal 5a, and turns a DC electromagnetic contractor 18 OFF upon detection of synchronization shift and provides a gate block signal 17a to the phase control circuit 7.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a control device for an electric motor, and particularly to a thyristor Leonard control device using a digital control method.

(Prior Art) As a conventionally widely used control method for a DC motor, there is thyristor Leonard control using a non-circulating current method. This control method performs control by switching between a forward and reverse thyristor converter connected to an armature circuit depending on the direction of torque required by the motor, and is known as an excellent method. Furthermore, in recent years, with the remarkable development of microcomputers, it has become desirable to digitize control devices. Therefore, single-chip microcomputers and the like have come to be widely used for phase control of thyristors of the thyristor Leonard type.

FIG. 4 is a block diagram showing an example of a conventional non-circulating current type thyristor Leonard device.

In the figure, 1 is a speed command generation circuit, 2 is a speed command generation circuit 1
4 is a current control circuit that outputs a current reference signal 2a corresponding to the motor generated torque command according to the deviation between the speed command signal 1a from the motor 9 and the speed signal 11a from the speed detector 11 coupled to the motor 9; In the circuit, the current reference signal 2a
According to the deviation of the current signal 3a obtained from the current detector 3 provided in the AC mains 1il12, a phase control reference signal 4a is output. Further, 6 is a power synchronization circuit, which receives a voltage signal 5a from an AC voltage detector 5 connected to the AC bus 12.
outputs a power synchronization signal 6a. A phase control circuit 7 outputs a firing command 7a to each thyristor of the thyristor converter 8 in accordance with a phase control reference signal 4a and a power synchronization signal 6a. As mentioned above, in recent years, this phase control circuit 7
1-chip microcontrollers are becoming widely used.

With this configuration, the speed of the electric motor 9 is controlled by the rectified output of the thyristor converter 8. In the figure, reference numeral 10 denotes a motor field winding, which is subjected to constant excitation or field weakening control depending on the application. Further, 13 is a DC electromagnetic contactor.

(Problems to be Solved by the Invention) When attempting to control a motor using a control device as shown in FIG.
is out of synchronization with respect to the AC bus, the phase control circuit 7
In this case, each thyristor of the thyristor converter 8 cannot be fired at the normal firing phase, and as a result, a control abnormality occurs in which overcurrent flows in the thyristor element or the motor, or overvoltage occurs.

SUMMARY OF THE INVENTION An object of the present invention is to provide an electric motor control device that can safely protect the entire control system when synchronization with the power supply occurs.

[Structure of the invention]

(Means for Solving the Problems) The present invention includes a thyristor converter that converts AC power from an AC power source into DC power to drive a motor, and gives an ignition command to the thyristor constituting this thyristor converter. A phase control means, a synchronization signal output means for providing an output signal synchronized with the phase of the AC power supply to the phase control means, and a detection of whether or not the output signal of the synchronization signal output means is synchronized with the phase of the AC power supply. The present invention is characterized by comprising a synchronization detection means for detecting synchronization, and a protection means for gate-blocking the thyristor and disconnecting the motor from the output side of the thyristor converter when a synchronization shift is detected by the synchronization detection means.

(Function) In the device configured as described above, the output signal of the synchronization signal output means is normally synchronized with the phase of the AC power supply, so the phase control means issues an ignition command to the thyristor based on this output signal. give to

When the output signal of the synchronization signal output means is out of phase with the phase of the AC power supply, the synchronization detection means detects this, and the protection means gate blocks the thyristor and disconnects the motor from the output side of the thyristor converter. .

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. 1st
In the figure, the same parts as in FIG. 4 are given the same reference numerals, and the explanation thereof will be omitted, and the different parts will be explained.

As shown in FIG. 1, this device has a power synchronization detection circuit 17 and an electromagnetic contactor excitation circuit 18 for releasing the electromagnetic contactor 13 added to the configuration shown in FIG. The power supply synchronization detection circuit 17 receives the voltage signal 5 which is the output of the AC voltage detector 5.
0, detects a synchronization shift with respect to the phase of the phase voltage of the AC power supply bus 12, and when a synchronization shift is detected, the DC magnetic contactor 1
A contactor off command signal is given to the excitation circuit 18 of No. 3, and a gate block signal 17a is given to the phase control circuit 7.

FIG. 2 is a circuit configuration diagram showing details of the configuration of the power synchronization detection circuit 17. In the figure, 19A to 19G are 60 degrees that delay each phase voltage signal from the voltage detector 5 by 60 degrees and output it.
Phase delay circuits (here, it is assumed that the alternator ma source is three-phase), 20A to 20G are provided corresponding to each 60° phase delay circuit 19A to IOC, and the output of the corresponding circuit Converts the 60° phase-lag voltage signal to logic “Hn” or “L” depending on its level and generates logic signal 2.
Logic detection circuit 21 is a fuse ROM (read-only memory) that outputs signals 0a to 20c, and the logic signals 20a to 20c are output to lower addresses (AO to 20c).
A2), and the frequency divided signal 2 from the frequency dividing circuit 25, which will be described later.
5a to 25d are connected to upper addresses (A3 to A6), and the voltage information and synchronization difference information stored in the addresses corresponding to the address signals are respectively sent to the voltage signal 2.
1a to 21c and output as a synchronization detection signal 17a (here, AO to 86 indicates the lowest address and 86 indicates the highest address), and the signal 21d is a voltage angle of 1800 divided by 12. This is a period division clear output for stopping the output, and is an output signal of the data output terminal D4 of the ROM 21. 22 is an adder that adds the voltage signals 21a to 21c; 23 is a voltage smoothing circuit that smoothes the added signal 22a;
24 is a voltage oscillation circuit (V, C.

This is a frequency dividing circuit that generates 8'4'2 frequency divided signals 25a to 25d.

Further, FIG. 3 is a timing diagram showing the output state of each element in FIG. 2 when the voltage detection signal is synchronized with the phase of the power supply bus voltage.

The above ROM21 stores the voltage level of each phase of U, V, and W in 2 times when there is no voltage abnormality or synchronization difference with respect to the phase of the power supply bus, and when 180 degrees of electrical angle is divided into 12 equal parts.
ty, v, which can be taken at this time as valued data,
V, C, O generated under constant voltage input when the binary data of each phase of w corresponds to the lower 3 bits of the address and there is no voltage abnormality or synchronization shift as described above.
When the pulse signal 24a of the circuit 24 is frequency-divided by the frequency dividing circuit 25 and the upper 4 bits are designated as addresses A3 to A6, the above U, V, and W are applied to each address that can be specified.
Data corresponding to each of the 12 equal sections of the binary data of the voltage level of each phase are stored. At this time U.

(2) Each phase of W is stored in correspondence with each of the data bit positions of the lower three bits. In addition, the fifth data bit from the lowest (D4) stores reset data "H'y" for giving a reset signal to the frequency divider circuit 25 at the address corresponding to the last section of the above 12 equal parts. 25 is reset by dividing the frequency by 12 unless there is an abnormality or a synchronization error in the power supply bus (as long as it is normal) to prevent further branching.

In addition, in order to deal with abnormalities, abnormality notification data "H" is stored in the fourth data bit (D3) from the bottom of addresses other than those that can be specified during normal times, and When an address is specified, abnormality notification data "H" is output from D3.

Next, the operation of this device having the above configuration will be explained.

In the present apparatus shown in FIG. 1, the operation of the power synchronization detection device 17 according to this embodiment will be explained in particular with reference to FIGS. 2 and 3. Note that in FIG. 1, detailed descriptions of the effects of other elements have already been given, so they will not be repeated here.

Now, in FIG. 2, when the voltage signals U, V, and W of each phase U, V, and W detected by the AC voltage detector 5 are input to the 60° phase delay circuits 19A to 19C, the 60° 1
The phase is delayed, and the signal is sent to the logic detection circuit 20A~
Depending on the level given to 20G, a logic “H” signal or 1g
L ## signal is converted and becomes output signals 20a to 20c. This state is shown in FIG. 3 (diagrams 0 to ■). Output signals 20a to
20c is used to specify the lower address of the ROM 21, and the upper address of the ROM 21 is specified by the output of the frequency dividing circuit 25, and when the stored data of this specified address is read, the adder 22 receives the data from the ROM 21. Of these, output data (voltage signals) 218 to 21c of data output terminals DO to D2 are added and the resulting signal 22a is provided to the voltage smoothing circuit 23. The voltage smoothing circuit 23 receives the above signal 22a.
Smooth the voltage oscillation circuit (hereinafter referred to as v).

(referred to as C, O) 24 is given a signal 23a. V.C.

024 outputs a square wave pulse with a frequency commensurate with the voltage 23a. Here, V, C, 024 generates a pulse (as shown in FIG. 3) with a frequency corresponding to the input voltage, and if the input voltage is constant, a pulse with a constant frequency is output. That is, when the output from the voltage smoothing circuit 23 settles down to a constant level, the output pulse signal 24 from V, C, 024
a becomes a pulse with a constant frequency.The 0 frequency divider circuit 25 receives this pulse signal 24a and divides it into a frequency-divided signal 25.
Generates a to 25d.

That is, when the pulse signal 24a settles down to a certain frequency, it is added to the pulse signal 24a, and 11 as shown in FIG.
By the way, the logic signals 20a to 20c and the frequency divided signals 25a to 25d are connected to the address line of the ROM 21, and this address signal The voltage signal 21
Output a to 21c. That is, the ROM performs RO mode for address modes "0" to "11" determined by the frequency division signals 25a to 25d and the frequency divider clear output 25d.
The data of 20a set to the lower address of M21 is transferred to the DO data line by rLJ or rHJ.

The ROM is set so as to output a signal as shown in FIG. 3 (10) as the signal 21a. In the diagram of FIG. 3 (10), the solid line indicates that the signal 20a is rL in each of the above modes.
The one-dot line at the time of J indicates the output state when the signal 20a is "H". Similarly, the data of 20b and 20c is transmitted to signals 21b and 21c by rLJ or rHJ according to each of the address modes (11) and (12) in FIG.
The ROM is set to output a signal such as ). Now, suppose that in the address mode ItOFl~"11", the voltage signals U, V, W are in the state as shown in Figure 3 (■) (that is, the logic signals 20a~20c are in the state as shown in Figure 3 ■~0). ), the ROM21 is set as described above, so the output signal 21 is
A to 21c have output waveforms as shown in FIG. 3 (14) to (16). Further, the signal 22a added by the adder 22 becomes as shown in FIG. 3 (17), and the signal 22a
is applied to V, C, 024 as a constant voltage 23a through the voltage smoothing circuit 23, and an output signal 24a of a constant frequency is outputted from V, C, 024 and applied to the frequency dividing circuit 25, resulting in the above-mentioned result. The frequency-divided signals 25a to 25d are output, and the address mode advances to "O"11 and then returns to "0".In this state, the voltage detection signal is synchronized with the phase difference between the phase voltages of the AC power supply bus. Therefore, since the address area is not specified in the event of an error, the data in D3 of the ROM 21 is "L".
The magnetic contactor excitation circuit 18, which receives this data as a signal 17a, remains off and the magnetic contactor 3 does not open.

Further, the phase control circuit 7 receiving this signal 17a does not generate a gate block signal to each thyristor of the thyristor converter 8.

For example, in the apparatus shown in FIG. 1, the voltage signals U, V, and W shown in FIG. 2 may become abnormal due to an abnormality in the voltage detector or the like while the thyristor converter 8 is in operation.

Logic circuits 20A to 20G in which the signal is out of synchronization with the phase of the phase voltage of the AC power supply bus and the voltage value of each phase is
When the output after passing does not follow the normal data pattern, for example, if 20a to 20c become all "H" or all "L", the address that can be specified in ROM 21 corresponds to an area outside the normal latitude. Therefore, since the data of D3 is "H" in this area, the signal 17a which is the output of D3 of the ROM becomes "H". That is, as described above, the ROM 21 receives voltage signals U, V, and W for each address mode.
It is used to specify the lower addresses AO to A2 of the ROM 21 through 0C. ), it is possible to recognize whether the signal is synchronized with the bus power supply depending on the state of the signals 20a to 20c.
When it deviates from the figure 3 ■～■, D3 of ROM21
The output signal 17a from the data output line becomes rHJ. This signal 17a is transmitted to the phase control circuit 7 in FIG.
and the electromagnetic contactor excitation circuit 18, thereby gate blocking the thyristor conversion device 8, and
Turn off the electromagnetic contactor 3 and disconnect the motor from the DC bus.

As a result of the above, when the phase of each phase voltage of the AC bus is out of synchronization or a voltage abnormality occurs, the thyristor converter 8 is gate blocked and the motor is disconnected from the DC bus. It is possible to protect the converter and, by extension, the entire system.

As described above, according to this embodiment, a forward/reverse thyristor converter 8 connected to a switchable armature circuit is disposed in the a source device according to the torque direction required by the motor,
In a thyristor Leonard device that controls the phase of a thyristor in a converter by obtaining a signal synchronized with the phase voltage of an AC power supply bus, even if the power supply synchronization signal 6a is out of synchronization with the phase of the power supply during control, the power supply Even if an abnormality occurs in
can be turned off and the electric motor 9 can be disconnected.

The converter and the control device of the entire system can be adequately protected.

〔Effect of the invention〕

According to the present invention, it is possible to provide an electric motor control device that can safely protect the entire control system when synchronization with the power source occurs.

[Brief explanation of the drawing]

1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing an example of the power synchronization detection circuit in FIG. 1, and FIG. 3 is a block diagram showing an example of the power synchronization detection circuit in FIG. FIG. 4, a timing diagram showing the operation, is a configuration diagram of a conventional thyristor Leonard device. 6... Power synchronization circuit, 7... Phase control circuit,
8... Thyristor converter, 9... Electric motor. 12... AC power supply bus, 13... Magnetic contactor, 17... Power synchronization detection circuit, 18... Magnetic contactor excitation circuit. Agent Patent Attorney: Nori Chika Ken Masaki Daikomaru Ken

Claims (1)

[Claims] A thyristor converter that converts AC power from an AC power supply into DC power to drive a motor, a phase control means for giving a firing command to a thyristor constituting this thyristor converter, and this phase control synchronization signal output means for providing an output signal synchronized with the phase of the alternating current power supply to the means; synchronization detection means for detecting whether the output signal of the synchronization signal output means and the phase of the alternating current power supply are synchronized; A motor control device comprising protection means for gate-blocking the thyristor and disconnecting the motor from the output side of the thyristor converter when a synchronization shift is detected by the synchronization detection means.