JPH0197498U - - Google Patents

Description

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a timing diagram showing a write operation of the embodiment shown in FIG. 1, and FIG. 3 is a block diagram showing a conventional example. 9... Memory cell array, 13... Column decoder, 14... Row decoder, 15... Write/read circuit, 16... Control circuit, 17... I
/O buffer, 18...Pulse generation circuit, 19...
...Address transition detection circuit, 20...Data transition detection circuit.

Claims (1)

[Scope of utility model registration request] In a semiconductor memory in which a plurality of memory cells composed of cross-connected MOSFETs are arranged between a plurality of bit lines and a plurality of word lines, a write control signal applied from the outside reaches a predetermined level. a control circuit that detects the write control signal and controls the write operation; a data transition detection circuit that operates when the write control signal reaches a predetermined level and detects that data applied from the outside has changed; and the write control signal; and a pulse generation circuit that generates a pulse for a predetermined period based on the detection output of the data transition detection circuit, and the word that is controlled by the pulse output of the pulse generation circuit and determined by address data applied from the outside. an address decoder that sets a line to a predetermined level for the predetermined period of time, and when the write control signal reaches the predetermined level and when the data changes after the write control signal reaches the predetermined level, the memory cell A semiconductor memory characterized in that writing is performed on the semiconductor memory.