JPS63149497U - - Google Patents
Info
- Publication number
- JPS63149497U JPS63149497U JP3917887U JP3917887U JPS63149497U JP S63149497 U JPS63149497 U JP S63149497U JP 3917887 U JP3917887 U JP 3917887U JP 3917887 U JP3917887 U JP 3917887U JP S63149497 U JPS63149497 U JP S63149497U
- Authority
- JP
- Japan
- Prior art keywords
- memory device
- storage means
- passage
- mask data
- control means
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000002401 inhibitory effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
Description
第１図は本考案の一実施例の構成を示す模式ブ
ロツク図。第２図ａおよびｂは第１図におけるデ
ータ入力制御回路の一例およびデータ出力制御回
路の一例を示すブロツク図。
１…メモリセルアレイ、２…データ入力制御回
路、３Ａ…行アドレスラツチ回路、３Ｂ…列アド
レスラツチ回路、４…行アドレスデコーダ、５…
列アドレスデコーダ、６…データ出力制御回路、
７…タイミング信号発生回路、８…マスクデータ
バツフア、９および１０…マスクデータレジスタ
、１５…ダイナミツクＲＡＭ。
FIG. 1 is a schematic block diagram showing the configuration of an embodiment of the present invention. 2A and 2B are block diagrams showing an example of the data input control circuit and an example of the data output control circuit in FIG. 1; FIG. DESCRIPTION OF SYMBOLS 1...Memory cell array, 2...Data input control circuit, 3A...Row address latch circuit, 3B...Column address latch circuit, 4...Row address decoder, 5...
Column address decoder, 6...data output control circuit,
7... Timing signal generation circuit, 8... Mask data buffer, 9 and 10... Mask data register, 15... Dynamic RAM.
Claims (1)
て、マスクデータを記憶する記憶手段と、該記憶
手段に記憶したマスクデータにともなつて入力デ
ータ中の所望ビツトの通過を禁止するか、または
／および出力データ中の所望ビツトの通過を禁止
する制御手段とを備えたことを特徴とするメモリ
装置。 (2) 記憶手段はレジスタであることを特徴とす
る実用新案登録請求の範囲第１項記載のメモリ装
置。 (3) 記憶手段はラツチ回路であることを特徴と
する実用新案登録請求の範囲第１項記載のメモリ
装置。 (4) 制御手段はスリーステートバツフアである
ことを特徴とする実用新案登録請求の範囲第１項
記載のメモリ装置。[Claims for Utility Model Registration] (1) In a readable and writable memory device, storage means for storing mask data and prohibition of passage of desired bits in input data along with the mask data stored in the storage means and/or control means for inhibiting passage of a desired bit in output data. (2) The memory device according to claim 1, wherein the storage means is a register. (3) The memory device according to claim 1, wherein the storage means is a latch circuit. (4) The memory device according to claim 1, wherein the control means is a three-state buffer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3917887U JPS63149497U (en) | 1987-03-19 | 1987-03-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3917887U JPS63149497U (en) | 1987-03-19 | 1987-03-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63149497U true JPS63149497U (en) | 1988-10-03 |
Family
ID=30852112
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3917887U Pending JPS63149497U (en) | 1987-03-19 | 1987-03-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63149497U (en) |
-
1987
- 1987-03-19 JP JP3917887U patent/JPS63149497U/ja active Pending
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