JPH0198237A - Method of mounting semiconductor device - Google Patents

Method of mounting semiconductor device

Info

Publication number
JPH0198237A
JPH0198237A JP62256547A JP25654787A JPH0198237A JP H0198237 A JPH0198237 A JP H0198237A JP 62256547 A JP62256547 A JP 62256547A JP 25654787 A JP25654787 A JP 25654787A JP H0198237 A JPH0198237 A JP H0198237A
Authority
JP
Japan
Prior art keywords
whiskers
electrodes
semiconductor element
onto
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62256547A
Other languages
Japanese (ja)
Inventor
Yukio Nakamura
幸男 中村
Susumu Umibe
海邊 進
Tadashi Aikawa
相川 忠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP62256547A priority Critical patent/JPH0198237A/en
Publication of JPH0198237A publication Critical patent/JPH0198237A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/328Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by welding
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007Surface contacts, e.g. bumps
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/072Connecting or disconnecting of bump connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/072Connecting or disconnecting of bump connectors
    • H10W72/07251Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/231Shapes
    • H10W72/234Cross-sectional shape, i.e. in side view
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241Dispositions, e.g. layouts

Landscapes

  • Electroluminescent Light Sources (AREA)
  • Wire Bonding (AREA)
  • Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)

Abstract

PURPOSE:To grow innumerable whiskers from the surface of a metallic film, and to join all electrodes completely by growing whiskers onto a substrate and thermocompression-bonding a bump formed onto a semiconductor element. CONSTITUTION:A land pattern 2 consisting of a copper foil is shaped onto the surface of a substrate 1 composed of glass epoxy, etc., and metallic films 3 composed of a metal, from which whiskers are easy to be generated, such as Sn are prepared to one parts on the land pattern 2 through a plating method. The metallic films 3 are left as they are for several hr in approximately 9.0% humidity at approximately 50 deg.C, and the whiskers 4 in several mum are grown from the surfaces of the metallic films 3. The whole surface is coated with a UV-cured resin coating 5. A semiconductor element 8 is aligned and superposed onto the resin coating 5 while a pattern surface is directed downward. Al electrodes 7 for connection to the outside are shaped onto the pattern surfaces in the semiconductor element 8, and metallic bumps 6 composed of Au, etc., for joining are formed onto the surfaces of the electrodes 7. The whiskers 4 are crushed by the bumps 6 through pressing by hold-down jigs 9 from the upper section of the semiconductor element 8, and the height of the whiskers 4 is equalized while all electrodes are connected through the whiskers.

Description

【発明の詳細な説明】 産業上の利用分野 本発明はコンピュータ等に用いられる半導体装置の実装
方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for mounting semiconductor devices used in computers and the like.

従来の技術 近年、電気製品は軽薄短小化に伴ない、それに実装する
I(jもDIPタイプからフラットパッケージに、さら
にはパッケージのないペアーチップが使われるようにな
った。そして、この中でICチップ電極と基板の電極と
を圧接し、その周囲には、UV硬化樹脂をコートし、固
着するタイプがある。
Conventional technology In recent years, as electrical products have become lighter, thinner, and smaller, the I(J) mounted on them has changed from DIP types to flat packages, and even pair chips without packages are now being used. There is a type in which the chip electrode and the electrode on the substrate are brought into pressure contact, and the periphery thereof is coated with UV curing resin and fixed.

発明が解決しようとする問題点 しかしながら、この方法では電極数が増え、ICチップ
サイズが大型化するとICチップ電極と基板電極とが水
平でなくなり、ギャップが発生し、圧接だけでは、接触
不良が発生するという問題点を有していた。
Problems to be Solved by the Invention However, with this method, as the number of electrodes increases and the IC chip size increases, the IC chip electrodes and substrate electrodes are no longer horizontal, creating a gap, and contact failure occurs when only pressure welding is used. There was a problem with this.

この問題を解決するため本発明はギャップが発生しても
確実に接触を補償するものである。
In order to solve this problem, the present invention reliably compensates for contact even if a gap occurs.

問題点を解決するための手段 この目的を達成するため基板上にホイスカーを成長させ
た後、基板を樹脂膜で覆い、半導体素子上に形成された
バンプを熱圧着によりボイスカーと接続するものである
Means for Solving the Problem To achieve this objective, whiskers are grown on a substrate, the substrate is covered with a resin film, and the bumps formed on the semiconductor element are connected to the voice car by thermocompression bonding. .

作用 この方法によりギャップがあっても、ホイスカーが半導
体素子上に形成されたバンプでつぶされるため、圧接に
よってホイスカーの当った所は押しつぶされ水平となり
、接触はホイスカーとで行なわれる。
In this method, even if there is a gap, the whiskers are crushed by the bumps formed on the semiconductor element, so the areas where the whiskers hit are crushed and become horizontal due to pressure contact, and contact is made between the whiskers and the whiskers.

実施例 以下、本発明の実施例について図面を参照して説明する
。第1図は本発明の一実施例における半導体装置の断面
図である。同図において、1は基板であり、2は基板1
上に形成されたランドパターン、3はランドパターン2
上に設けられた金属膜、4はホイスカー、6は半導体素
子8の五l電極7上に形成されたバンプである。
Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention. In the figure, 1 is a substrate, and 2 is a substrate 1.
Land pattern formed on top, 3 is land pattern 2
The metal film provided above, 4 is a whisker, and 6 is a bump formed on the electrode 7 of the semiconductor element 8.

以下、その製造方法について第2図〜第6図を用いて説
明する。
The manufacturing method will be described below with reference to FIGS. 2 to 6.

実装゛しようとするガラスエポキシ等の基板1の表面に
銅箔のランドパターン2が形成されており、その上の一
部にホイスカーの発生しやすい金属例えばSnの金属膜
3をメ・フキ法にて作成する(第2図)。
A land pattern 2 of copper foil is formed on the surface of a substrate 1 made of glass epoxy or the like to be mounted, and a metal film 3 of a metal that tends to generate whiskers, such as Sn, is formed on a part of the land pattern 2 using the foil method. (Figure 2).

次にこれを約50’C,湿度約9.0qbで数時間放置
し、金属膜3の表面よりホイスカー4を数μ成長させる
(第3図)。この後、表面全体をUV硬化の樹脂コート
6で覆う(第4図)。さらに、この上に半導体素子8を
パターン面を下にして位置を合わせ重ねる。半導体素子
8のパターン面には外部との接続のためAd電極7があ
り、この表面に接合用のムU等の金属バンプ6がメツキ
法や転写方式によって形成されている。このようにして
半導体素子8の上より押え治具9で加圧するとボイスカ
ー4はバンプ6で押しつぶされ、一定の高さになるとと
もに全電極がホイスカーを介して接続される。
Next, this is left for several hours at about 50'C and a humidity of about 9.0 qb, and whiskers 4 are grown by several micrometers from the surface of the metal film 3 (FIG. 3). Thereafter, the entire surface is covered with a UV-curable resin coat 6 (FIG. 4). Furthermore, the semiconductor element 8 is positioned and stacked on top of this with the pattern surface facing down. There is an Ad electrode 7 on the patterned surface of the semiconductor element 8 for external connection, and metal bumps 6 such as bumps for bonding are formed on this surface by a plating method or a transfer method. When pressure is applied from above the semiconductor element 8 with the holding jig 9 in this way, the voice car 4 is crushed by the bumps 6 and reaches a constant height, and all the electrodes are connected via the whiskers.

次に、この状態でUV光を照射して樹脂を硬化させる。Next, in this state, UV light is irradiated to harden the resin.

この後ICチップ8の保護および信頼性の点から全体に
樹脂外装コート1oをする。
Thereafter, a resin exterior coat 1o is applied to the entire IC chip 8 from the viewpoint of protection and reliability.

発明の効果 以上のように本発明は電極間のギャップがあっても、ホ
イスカーが金属膜の表面より無数成長し、これを押しつ
ぶす形で接触させるため全電極は完全に接合することが
出来る。このため大型チップや電極数の多いI(3チフ
プにはより有効である。
Effects of the Invention As described above, in the present invention, even if there is a gap between the electrodes, the whiskers grow in large numbers from the surface of the metal film and are pressed into contact with each other, so that all the electrodes can be completely joined. Therefore, it is more effective for large chips and I (3 chips) with many electrodes.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例における半導体装置の断面図
、第2図〜第5図は同裂造工程を示す断面図である。 1・・・・・・基板、2・・・・・・ランドパターン、
3・・・・・・金属膜、4・・・・・・ホイスカー、6
・・・・・・樹脂コート、6・・・・・・バンプ、7・
・・・・・ムlt極、8・・・・・・ICチップ、9・
・・・・・押え治具、1o・旧・・樹脂外装コート。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名4−
一−ボ54又刀− 8−v絹本系あ
FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention, and FIGS. 2 to 5 are sectional views showing the same fabrication process. 1... Board, 2... Land pattern,
3... Metal film, 4... Whisker, 6
...Resin coat, 6...Bump, 7.
...Mult pole, 8...IC chip, 9.
...Press jig, 1o, old...resin exterior coat. Name of agent: Patent attorney Toshio Nakao and 1 other person 4-
1-Bo 54 Matata- 8-v Silk book series

Claims (1)

【特許請求の範囲】[Claims]  基板上にホイスカーを成長させた後、基板を樹脂膜で
覆い、半導体素子上に形成されたバンプを熱圧着により
ホイスカーと接続することを特徴とする半導体装置の実
装方法。
A method for mounting a semiconductor device, which comprises growing whiskers on a substrate, covering the substrate with a resin film, and connecting bumps formed on a semiconductor element to the whiskers by thermocompression bonding.
JP62256547A 1987-10-12 1987-10-12 Method of mounting semiconductor device Pending JPH0198237A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62256547A JPH0198237A (en) 1987-10-12 1987-10-12 Method of mounting semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62256547A JPH0198237A (en) 1987-10-12 1987-10-12 Method of mounting semiconductor device

Publications (1)

Publication Number Publication Date
JPH0198237A true JPH0198237A (en) 1989-04-17

Family

ID=17294154

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62256547A Pending JPH0198237A (en) 1987-10-12 1987-10-12 Method of mounting semiconductor device

Country Status (1)

Country Link
JP (1) JPH0198237A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5877833A (en) * 1990-09-10 1999-03-02 U.S. Philips Corporation Interconnection structure with raised perimeter portions
US20150221842A1 (en) * 2012-12-21 2015-08-06 Panasonic Intellectual Property Management Co., Lt Electronic component package and method for producing same
US9425122B2 (en) 2012-12-21 2016-08-23 Panasonic Intellectual Property Management Co., Ltd. Electronic component package and method for manufacturing the same
US9449944B2 (en) 2012-12-21 2016-09-20 Panasonic Intellectual Property Management Co., Ltd. Electronic component package and method for manufacturing same
US9595651B2 (en) 2012-12-21 2017-03-14 Panasonic Intellectual Property Management Co., Ltd. Electronic component package and method for manufacturing same
JP2018195642A (en) * 2017-05-15 2018-12-06 富士通株式会社 Semiconductor device and manufacturing method of semiconductor device
CN114567969A (en) * 2020-11-27 2022-05-31 万润科技股份有限公司 Electronic component back film method and device

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5877833A (en) * 1990-09-10 1999-03-02 U.S. Philips Corporation Interconnection structure with raised perimeter portions
US20150221842A1 (en) * 2012-12-21 2015-08-06 Panasonic Intellectual Property Management Co., Lt Electronic component package and method for producing same
US9425122B2 (en) 2012-12-21 2016-08-23 Panasonic Intellectual Property Management Co., Ltd. Electronic component package and method for manufacturing the same
US9449944B2 (en) 2012-12-21 2016-09-20 Panasonic Intellectual Property Management Co., Ltd. Electronic component package and method for manufacturing same
US9595651B2 (en) 2012-12-21 2017-03-14 Panasonic Intellectual Property Management Co., Ltd. Electronic component package and method for manufacturing same
US9825209B2 (en) * 2012-12-21 2017-11-21 Panasonic Intellectual Property Management Co., Ltd. Electronic component package and method for manufacturing the same
JP2018195642A (en) * 2017-05-15 2018-12-06 富士通株式会社 Semiconductor device and manufacturing method of semiconductor device
CN114567969A (en) * 2020-11-27 2022-05-31 万润科技股份有限公司 Electronic component back film method and device
CN114567969B (en) * 2020-11-27 2023-08-08 万润科技股份有限公司 Electronic component back film method and equipment

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