JPH0199313A - Pulse generator for variable low frequency pulse width - Google Patents

Abstract

PURPOSE:To improve the operability of a frequency setting switch by making the setting value of the frequency setting switch coincident with an output frequency. CONSTITUTION:A count setting value of a commercial frequency pulse FO corresponding to an output frequency is stored in advance in a memory and a setting value of a frequency setting switch 4 is read in a CPU 5 and the count setting value in the memory corresponding to the setting switch data is given to a counter circuit 3 from the CPU 5 to make the output frequency coincident with the setting value of the frequency setting switch 4. The output frequency is set independently of number of digits of the frequency setting switch 4 to provide general application to the switch 4 by the data change in the memory. Moreover, as to the pulse width, the pulse width is changed optionally by using a digital signal through the use of a reference clock using the reference oscillator, the counter circuit and the pulse width setting switch.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a device that generates a pulse width of a variable low frequency that is a step down from a commercial frequency, and particularly to a device that allows frequency and pulse width to be easily and precisely set using digital values. Note that in the following figures, the same reference numerals indicate the same or corresponding parts. Also logic or level “High”, “L”
ow" shall be simply written as 11 HII, II L".

[Conventional technology]

FIG. 3 is a circuit example of a conventional low frequency medium pulse generator of this type. In the figure, the voltage of a commercial power supply 1 is applied to a zero cross detection circuit 2 via a transformer TR to obtain a commercial frequency pulse FO as a rectangular wave pulse of the commercial power supply frequency, and then the pulse FO is input as a clock input to a counter circuit 3. Input to terminal CK. The counter circuit 3 counts the commercial frequency pulse FO, and the counted value is determined by the frequency setting switch 4.
When the value is set by and matches the value given to the terminal of the counter circuit 3, a low frequency pulse F1 is output as a match signal. This low frequency pulse F1 is then given to the monostable circuit MS as a trigger pulse. As a result, the monostable circuit MS maintains its output Q from the conventional "L" level to the "HT level" for a period determined by the capacitor C1 and resistor R1 attached to it, and similarly changes its output page from the conventional "L" level to the "HT level". Change from "H" level to "L level" and hold. Note that the signal of the change of the output page from "H" to "L" is applied to the counter circuit 3 via the reset circuit PS, and this counter circuit 3 is reset. As a result, the counter circuit 3 repeats the above operation from the beginning. That is, the circuit shown in Fig. 3 generates a low frequency pulse whose width is determined by the frequency setting switch 4 and which is lowered from the commercial frequency, and the time width of the width pulse is determined by the capacitor CI and the resistor R1. .

[Problems to be solved by the invention]

However, the apparatus shown in FIG. 3 has the following problems. First, the frequency of the low-frequency pulse F1 (download frequency) does not match or is proportional to the set value of the frequency setting switch 4. This is because the down-down frequency is proportional to the reciprocal of the setting value of the setting switch 4. Therefore, if the commercial frequency is 607, to obtain a down frequency IHz, set the setting switch 4 to 60, and to obtain a down frequency 27, set the setting switch 4 to 30. calculation of the setting value of the frequency setting switch 4 is troublesome, and setting errors are likely to occur. Second, the output frequency is limited by the number of digits in the setting switch 4. In other words, in the case of 3 digits, the number of digits in the setting switch 4 is 1 to 99.
9 is the setting data, but the output frequency (down frequency) is 607 (1 setting) to 0.067 (999 setting),
Therefore, if an output of 0.0 IHz is required, four digits are required, so a general-purpose setting switch cannot be used. Thirdly, the pulse width is determined by the product of the capacitor CI of the monostable circuit MS and the resistor R1, and the pulse width is changed by using the resistor R1 as a variable resistor.
It is limited by the value of resistor R1. Furthermore, since the setting is performed while checking by waveform observation, the accuracy of setting the pulse width is poor. The purpose of the present invention is to set the setting value of the frequency setting switch 4 by the CPU.
By converting the pulse width into the counter 3 and determining the pulse width as the counting time of the clock pulse, there is an advantage that the set value of the frequency setting switch 4 matches the output frequency, and the number of digits of the setting switch On the other hand, it is possible to set the required output frequency regardless of the pulse width, and furthermore, it is possible to easily set the required pulse width using a switch for setting the pulse width without observing the waveform.

[Means to solve the problem]

In order to achieve the above object, the device of the present invention uses a commercial frequency (pulsed FO)
A variable low frequency medium pulse generator equipped with a low frequency pulse output means (such as the counter circuit 30) that continuously repeats the operation of outputting a pulse (such as Fl, hereinafter referred to as a low frequency pulse) every time a first set number is counted. The device includes a frequency setting means (frequency setting switch 4, etc.) that sets a numerical value proportional to the frequency of the low-frequency pulse, and inputs the numerical value, refers to data in a memory (ROM 8.9, etc.), and sets this value. a CPU (such as 5) that supplies the first set number corresponding to a numerical value to the low frequency pulse output means; a clock pulse generation means (such as a reference clock generation circuit IO) that generates a clock pulse of a predetermined frequency; pulse width setting means (pulse width setting switch 71, etc.) for setting a second setting number corresponding to the width; Width pulse output means (flip-flop 61, counter circuit 31.A
ND gate AC1, etc.).

[For use]

This invention provides a commercial frequency pulse F corresponding to the output frequency.
The count setting value of O is stored in memory in advance, and the CPU
Load the setting value of the frequency setting switch into this CP.
The count setting value in the memory corresponding to the setting switch data is given from U to the counter circuit 3 so that the output frequency and the setting value of the frequency setting switch can be matched, and by changing the data in the memory. The frequency setting switch has versatility by allowing the output frequency to be set regardless of the number of digits of the frequency setting switch. Furthermore, the pulse width can be arbitrarily changed digitally using a reference clock using a reference oscillation element, a counter circuit, and a pulse width setting switch.

【Example】

FIG. 1 is a circuit diagram showing a main part configuration as an embodiment of the present invention, and corresponds to FIG. 3, and FIG. 2 is a time chart for explaining the operation of FIG. 1. In FIG. 1, the voltage of a commercial power supply 1 (FIG. 2 (1)) is passed through a zero-cross detection circuit 2 to a commercial frequency pulse FO (
2 (2)) and this pulse FO is given to the counter circuit 3 (30) for counting, which is the same as in FIG. 3, but the difference between FIG. 1 and FIG. The count set value is input to the terminal of the counter circuit 30 not directly using the frequency setting switch 4, but via the CPU 5, and the output pulse from the counter circuit 30 (low frequency pulse) A circuit that sequentially outputs medium pulses P (Pi to P5) using Fl as a trigger signal (clock signal) is composed of flip-flops 6 (61 to 65), counter circuits 3 (31 to 35), and pulse width setting switches 7 (71 to 71).
75), reference clock generation circuit 10. AND game) AG
This point is composed of I to AG5. ROM data DTI and DT2 in Figure 1 are each CP
An example of setting data in ROM8.9 attached to U5 is shown, and addresses 1, 2, 3.4 . −
・The setting data of 60.30.20°15.- at the address is 1.2, 3.4.- each low frequency pulse F.
This is the count setting value corresponding to 1. Similarly, ROM data D
Address of T2, 600, 300, 200, 150 at address 1゜2.3.4-... - setting data are 0.1.0.2.0.3.0.4 respectively. . . . is a count setting value corresponding to each low frequency pulse F1. The CPU 5 reads the frequency setting value of the frequency setting switch 4 (in this example, it is a 2-digit decimal value), and stores the count setting value corresponding to the frequency setting value in the ROM 8. Alternatively, it is obtained from 9 and applied to the count setting value input terminal of the counter circuit 30. Therefore, for example, if you specify in advance to refer to the ROM 8 using a setting means not shown in the figure, and set the frequency setting switch 4 to 1 or 3, the CPU 5 will set the setting data 60 or 2 at address 1 or 3 of the ROM 8. is applied to the counter circuit 30, and the counter circuit 30 outputs a low frequency pulse F1 of 17 or 3H2. If the ROM 9 is specified to be referenced at this time, the CPU 5 gives the setting data 600 or 200 of the 1st or 3rd address of the ROM 9 to the counter circuit 30, and the counter circuit 30 outputs a low frequency of 0.1 & or 0.3 Hz. Outputs frequency pulse F1. That is, there is a proportional relationship between the frequency of the low frequency pulse F1 and the setting value of the frequency setting switch 4, and the setting is easy to understand and there is little chance of setting errors. In this way, in this example, low frequency pulses F1 of 0.17 to 9.97 can be obtained by ROM data DTI and the same (0.17 to 9.97 by DT2). The operation of the width pulse output circuit will be described.The low frequency output pulse F1 is connected to the clock input terminal CK of the flip-flop 61.
and the output Q of the flip-flop 61 is “L”.
to "H", and the same output page changes from "H" to "L II". As a result, the gate of the AND gate (AGI) which newly inputs the output Q of "H" is opened, and the reference clock generation circuit 1
A clock pulse lOa of 0 is input to the clock input terminal CK of the counter circuit 31, and the counter circuit 31 starts counting this clock pulse 10a. Further, the new output page of "L" resets the counter circuit 3o via the reset circuit PS, and the counter circuit 30
starts counting the commercial frequency pulses FO again from the beginning. Now, when the count value of the counter circuit 31 reaches the count setting value input from the pulse width setting switch 71 to the terminal of the counter circuit 31, the counter circuit 31 outputs a coincidence pulse from its terminal UD. This coincidence pulse is applied to the reset terminal of the flip-flop 6E, and the output Q of the flip-flop 61 is "l L
I+, the same output page returns to the H' state. By this change of output Q from “H” to “L” at the time of reset, AND
The gate AGI is closed, the counter circuit 31 stops counting, and at the same time, the output Q of the flip-flop 62 in the next stage is inputted to the clock input terminal CK.
is newly set to "H'", and the counter circuit 32 at the next stage starts counting operation in the same way as the counter circuit 31 described above. In this way, the operations of flip-flops 62 to 65 are repeated in sequence in the same manner as flip-flop 61, resulting in flip-flops 61, 62, 64, 65, . Width pulse output P(PI,
P2. P4. P5) becomes as shown in FIG. 2 (3) to (6). Here, each time width of t1 to t5 is proportional to the set value of the pulse width setting switches 71 to 75, respectively.

【Effect of the invention】

According to the present invention, the counter circuit 30 continuously repeats the operation of outputting a pulse (hereinafter referred to as a low frequency pulse) Fl every time the commercial frequency pulse FO is counted by the first set number given to the terminal. In the variable low frequency submerged pulse generator, there is a frequency setting switch 4 for setting a numerical value proportional to the frequency of the low frequency pulse F1, and inputting the numerical value and referring to data in the ROM 8.9.
The CPU 5 gives the first set number corresponding to this numerical value to the counter circuit 30, the reference clock generation circuit 10 generates the clock pulse 10a of a predetermined frequency, and sets the second set number corresponding to the pulse. The pulse width setting switch 71 and each output of the low frequency pulse F1 set the low frequency pulse F1.
a flip-flop 61 that outputs a width pulse that lasts from the output point of 1 until the clock pulse is counted by the second set number; Counter circuit 31. Since the AND gate AG1 is provided, the setting value of the frequency setting switch 4 and the output frequency (frequency of the width pulse output P)
coincide with each other, improving the operability of the frequency setting switch and reducing setting errors, and the output frequency can be easily changed using ROM data if necessary. Furthermore, since the pulse is digitally set, the setting accuracy can be improved.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing the main part configuration as an embodiment of the present invention, Fig. 2 is a time chart for explaining the operation of Fig. 1, and Fig. 3 is a conventional circuit diagram corresponding to Fig. 1. be. 1: Commercial power supply, 2: Zero cross detection circuit, 3 (30 to 3
5): Counter circuit, 4: Frequency setting switch, 5:
CPU, 6 (61-65): flip-flop,
7: (71-75): Pulse width setting switch, 8
, 9: ROM5 ACI~AG5: AND gate, 10: Reference clock generation circuit, FO: Commercial frequency pulse, Fl: Low frequency pulse, P (Pi~P5): Width pulse output.

Claims (1)

[Scope of Claims] 1) A variable low frequency width provided with a low frequency pulse output means that continuously repeats an operation of outputting a pulse (hereinafter referred to as a low frequency pulse) every time a first set number of commercial frequencies are counted. The pulse generator includes a frequency setting means for setting a numerical value proportional to the frequency of the low-frequency pulse; A CPU for supplying the low frequency pulse to the low frequency pulse output means; a clock pulse generating means for generating a clock pulse of a predetermined frequency; a pulse width setting means for setting a second set number corresponding to the pulse width; and an output of the low frequency pulse. variable width pulse output means for outputting a width pulse that lasts from the time when the low frequency pulse is output until the clock pulse is counted by the second set number. Low frequency width pulse generator.