JPH02100149A - Microcomputer - Google Patents

Abstract

PURPOSE:To reduce the number of steps of a program by adding an address circuit dedicated for memory on a microcomputer having a large number of memories, and attaching an increment function on the address circuit. CONSTITUTION:A microprocessor 1 transfers the address of the memory 2 to an address means 3 to make address to the memory 2 first, and next, transfers it to the memory 2. Data from the processor 1 is written on the address of the memory 2 designated by the address means 3, and after the operation is performed, the address means 3 increments the address of the memory 2. When the microprocessor 1 transfers the data to the memory 2 against, the address of the memory 2 at this time data been incremented by one address. The program can be generated without being conscious of the address of the memory 2 by making access to the memory 2 by repeating such operation. In such a way, it is not required to perform a complicated incrementing operation by the program, and it is possible to reduce the number of steps of the program, and to make the program easy to generate.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microcomputer, and more particularly to a memory address circuit that has a large amount of memory and has the function of frequently repeating memory access.

[Conventional technology]

Conventionally, this type of microcomputer has specified each memory address one by one when accessing the memory.

In particular, when using a 4-bit microphone computer and accessing memory continuously from the lower address to the upper address, the memory address is incremented by 4 bits (+1 addition), and the memory 9 address exceeds 4 bits. If so, increment the lower 4 bits, determine whether there is an up digit, then increment the upper 4 bits, determine whether there is an up digit, and then increment the upper 4 bits. The memory address was calculated by repeating increments of 4 bits at a time.

[Problem to be solved by the invention]

The above-mentioned conventional memory address means has a drawback that if it has a large amount of memory and is accessed frequently, the address calculation requires a number of program steps and is difficult to program.

[Means to solve the problem]

memory means accessed by the microprocessor means; and addressing means for addressing the memory means accessed by the microprocessor means; It has a function to increment the address of .

In this way, the present invention has address hardware that automatically increments when memory is accessed (read or written), so the program does not need to perform complex increment operations, and the number of steps in the program can be reduced. This makes it easier to create programs.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

The microprocessor 1 first transfers the address of the memory 2 to the address means 3 for addressing the memory 2, and then transfers the data to the memory 2. Data from the processor 1 is written to the address of the memory 2 specified by the address means 3. After this operation, the address means 3 increments the address of the memory 2.

Again, when microprocessor 1 transfers the memory 2 hetator, the address of memory 2 is incremented by one address from the previous time.

By repeating these operations and accessing the memory 2, a program can be created without being aware of the address of the memory 2.

Conversely, when data is transferred from the memory 2, a similar address operation can be performed.

(See Figure 2).

The address circuit 3 has an address latch 3-1 and an incrementer 3-2, as an example of its configuration is shown in FIG. A start address is latched into the address latch 3-1 from the processor 1 via the data bus 4. The outputs of latches 3-1 are incremented by incrementer 3-2 every time memory access request signal 5 is received from processor 1, and transferred to latch 3-1.

FIG. 3 shows another configuration of the address circuit 3.

The latch 3-1 latches an address that can also be called a start address, and the latches 3-.3 latch an address that can also be called a stop address. These two addresses can be set by the microprocessor means 1 via the data bus 4. Then, data is transferred by accessing the memory 2 from the start address of the latch 3-1, and when the start address is sequentially incremented by the incrementer 3-2 and reaches the initially set stop address of the latch 3-3, The coincidence detection circuit 3-4 interrupts the microprocessor means 1. With this configuration, meaningful data can be transferred between the start 7F address and the stop address, making it easier to create a program.

〔Effect of the invention〕

As explained above, the present invention is a microcomputer with a large amount of memory, and by adding an address circuit dedicated to the memory and adding an increment function to the address circuit, for example, an external asynchronous signal can be read and stored in the memory. When storing, if we consider the flow of first setting the memory address, then reading the external signal, and storing the external signal in memory, there is no need to program the memory address set. (The number of steps can be reduced to a maximum of 2/3) or this has the effect of allowing external signals to be read at high speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG.
FIG. 3 is a block diagram showing an example of the configuration of each address means. 1...Microprocessor means, 2...
・Memory means, 3...Address means. Agent Patent Attorney Susumu Uchihara

Claims (1)

[Claims] memory means accessed by the processor means; and address means for addressing the memory means accessed by the processor means; A microcomputer characterized by having an increment function.