JPH0210450B2 - - Google Patents

Info

Publication number
JPH0210450B2
JPH0210450B2 JP57208862A JP20886282A JPH0210450B2 JP H0210450 B2 JPH0210450 B2 JP H0210450B2 JP 57208862 A JP57208862 A JP 57208862A JP 20886282 A JP20886282 A JP 20886282A JP H0210450 B2 JPH0210450 B2 JP H0210450B2
Authority
JP
Japan
Prior art keywords
signal
carry
mos transistor
borrow
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57208862A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5999541A (ja
Inventor
Shigetatsu Katori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP57208862A priority Critical patent/JPS5999541A/ja
Publication of JPS5999541A publication Critical patent/JPS5999541A/ja
Publication of JPH0210450B2 publication Critical patent/JPH0210450B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
    • G06F7/503—Half or full adders, i.e. basic adder cells for one denomination using carry switching, i.e. the incoming carry being connected directly, or only via an inverter, to the carry output under control of a carry propagate signal

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
JP57208862A 1982-11-29 1982-11-29 算術論理演算回路 Granted JPS5999541A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57208862A JPS5999541A (ja) 1982-11-29 1982-11-29 算術論理演算回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57208862A JPS5999541A (ja) 1982-11-29 1982-11-29 算術論理演算回路

Publications (2)

Publication Number Publication Date
JPS5999541A JPS5999541A (ja) 1984-06-08
JPH0210450B2 true JPH0210450B2 (de) 1990-03-08

Family

ID=16563345

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57208862A Granted JPS5999541A (ja) 1982-11-29 1982-11-29 算術論理演算回路

Country Status (1)

Country Link
JP (1) JPS5999541A (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4685079A (en) * 1984-12-14 1987-08-04 Rca Corporation Ripple-borrow binary subtraction circuit
JP2616017B2 (ja) * 1989-06-19 1997-06-04 日本電気株式会社 ダイナミック演算装置

Also Published As

Publication number Publication date
JPS5999541A (ja) 1984-06-08

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