JPH02105232A - Method for verifying operation of logic circuit - Google Patents

Abstract

PURPOSE:To clearly handle the transition of the output state of each logic element and to accurately detect respective part where malfunction due to the deviation of timing occurs by performing minimum delay logical simulation and maximum delay logical simulation simultaneously. CONSTITUTION:In the verification of the operation a logic circuit, control for a simulation time, the control for repetition, and the generation of a pair of impression test vector events are performed first. Next, after the evaluation of the logic element is performed based on the minimum delay information and the maximum delay information supplied to each element in the logic circuit, the evaluation of a typical value is performed from logical simulation due to both delay. A various kind of verification in the logic circuit and the list output processing of a verification result, etc., are performed by using an output state table 702 based on the above evaluation, and such operations are repeated until the logical simulation is completed. In such a manner, it is possible to clearly handle the transition of the output state of each logic element and to accurately detect the part where the malfunction occurs due to the deviation of the timing, and also, to dispense with the unclear definition of the operation of the logic element for a transient state, etc.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method for verifying the operation of logic circuits, and in particular to LSIW.
The present invention relates to a method for verifying the operation of a logic circuit in which the logic operation based on the maximum and minimum delay times within each circuit in the iA logic circuit and its temporal operation are verified using a logic simulation method.

[Conventional technology]

Conventionally, the method of analyzing the operation of an 11i logic circuit after completion of gate-level logic design is to analyze the logic on an electronic computer using the truth value or functional description of the logic operation and M delay time information for the logic operation Express the circuit model as a data structure.

A logic simulator is used to verify the logical operation of the given applied test vector.

In particular, for the 1c71J-tube/70-tube element (hereinafter referred to as F'F/F element), the time interval (set γ-tube time) between the determination of the data signal and the clock operation, and the data signal after the clock operation is completed. Since the operation of the flip-flop is not guaranteed on the actual circuit unless the time interval (hold time) until it is possible to change is longer than the specified time, even in conventional logic simulation, each F/F element in the logic circuit is It also checks the set-up time and hold time specified for.

FIG. 8 is a flowchart of a conventional logic circuit operation verification method. It is assumed that the logic circuit has a data structure similar to the data structure on the computer shown in FIG. Logic simulation for operation verification is the 8th
The process starts from step 801 in the figure. Further, this simulation is performed using an appropriate time unit set in advance. Step 810 is means for performing time control in this logical simulation, and also performs repetitive control shown in the figure), and step 811 determines the end time of the logical simulation. If the end time has not been reached, step 820 generates an event based on the applied test vector for the time specified in step 810 and provides the generated event to the logic circuit.
It is.

Based on this test vector, the output state of each logic element is evaluated in step 830 using a predetermined delay time for each logic element, and the event is propagated throughout the logic circuit. In step 860, various types of operation verification are performed based on the results of this logic simulation, and necessary verification result information is output from the computer in the form of a list or the like. Then, the process returns to step 810 again, the time is advanced to the next unit, and the logic simulator 1 continues. If the end time has been reached, the process branches from step 811 to step 870 to perform necessary end processing, and in step 880 this logic simulation ends.

[Problem to be solved by the invention]

In the operation analysis of logic circuits using conventional logic simulations as mentioned above, we try to give each element the minimum value, maximum value, or typical value of the delay time. Usually, each element has only -a+ of the given delay time.

Therefore, for example, the results of a simulation using the minimum delay time and the results of a simulation using the maximum delay time do not necessarily match due to the difference in timing of signal propagation within the logic circuit. In particular, in logic circuits including sequential circuits, when a discrepancy in simulation results occurs due to this timing shift, subsequent simulations are also greatly affected by this discrepancy, causing a reduction in the reliability of the simulation results. This malfunction may occur in an actual circuit, and the same simulation method can be used to investigate the cause, but if you simply want to compare and examine the individual simulation results for each delay time, you will need to rely on human labor. A particular problem is that large-scale logic circuits require a great deal of effort.

Furthermore, in the min-max delay simulation method, a logic circuit is simulated using a given minimum delay time and maximum:M delay time. In this case, when the output state of each element changes, the logical value for the transition time range from the minimum delay time to the maximum delay time cannot be determined as 0 or 1, so the state of uncertain value (usually represented by X) is It is impossible to clearly distinguish between a transition state and an uncertain state. Therefore, with this means, malfunction of the circuit due to the timing difference K between the minimum delay and the maximum delay is also in an uncertain state, but there is a problem that it is difficult to specify the malfunction location on the logic circuit.

Furthermore, there is a logic simulation method that adds rising (6) and falling (target states) to the transition from logic value 0 to 1 or from 1 to O as a state value, but there is a truth table that defines the operation of the logic element. In the creation of circuits, it is not possible to provide clear definitions that correspond to actual circuits, and the focus is solely on logical consistency.

An object of the present invention is to provide a minimum delay time and a maximum delay time to each element of the logic simulator 1 part in a logic circuit, and to simultaneously perform logic simulation for both delay times, thereby reducing the output of each logic element. An object of the present invention is to provide a method for verifying the operation of a logic circuit, which enables clear handling of state transitions and detection of malfunctions due to timing deviations, and which eliminates the need for unclear operation definitions of logic elements for transition states, R, F, etc. be.

[Failure to solve the problem]

The method for verifying the operation of a logic circuit according to the present invention is characterized in that, in analyzing the logic operation of a logic circuit after gate-level logic design is completed, the connection relationship of each element in the logic circuit and the minimum delay that is an index of the operating speed of each element. Information on time and maximum delay time is constructed as a data structure in a storage area on an electronic computer, and logic simulation using the minimum delay time and logic simulation using the maximum delay time are performed based on test vector information applied to the logic circuit. and a typical value calculation means for calculating the typical value of each element in the logic circuit from these two logic simulations, The logic operation of each element in the logic circuit and its temporal operation are analyzed from the values.

〔Example〕

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a flow chart of the present invention. It is assumed that the argument circuit is constructed in advance on a computer using a data structure shown in FIG. 7, which will be described later. Logic simulation starts from step 101 in FIG. Step 110. IIIK controls the simulation time and also controls the repetition shown in the figure. Step 120 is a means for generating an event pair, which will be described later, based on the applied test vector and applying it to the input pin of the logic circuit.

Logic simulation uses this information to propagate events through the logic circuit from the input pins. This event propagation is based on the minimum delay information and maximum delay information given to each element in the logic circuit, step 130.
and 140.

Step 150 is a means for evaluating typical values from the logic simulation using both delays. Step 160 is a means for performing various verifications within the logic circuit and outputting a list of the verification results based on the above evaluation. Above steps 120, 130, 140° 150.160
is repeated in steps 110 and 111 until the end time of the logic simulation, necessary termination processing is performed in step 170, and the process ends in step 180.

Next, terms used in the detailed description are defined as follows.

The term "event" is used in the conventional sense of a logic state transition that occurs at the output pin of a device in a logic argument. As shown in Figure 1, in this logic circuit operation verification method, the minimum delay logic simulation and the maximum delay logic simulation are performed simultaneously, so events generated from each logic element usually occur in pairs from the two-wheel simulation. It is.

1) An event pair is an event that occurs from a logic element due to the same cause in both the minimum and maximum delay logic shimmy ranges.

2) A regular event pair is one in which both events of an event pair that occur from a certain logic element indicate a transition to the same logic state.

3) A non-regular event pair is a non-regular event pair.

That is, they are event pairs indicating transitions to different logical states.

Note that in both minimum delay and maximum delay wheel steering simulations, a timing shift occurs, so event pairs do not always occur.

4) An isolated event is an event that does not form an event pair.

5) Minimum isolated event refers to an isolated event that occurs in minimum delay logic simulation.

6) Transition time range refers to the time range from the occurrence of the smallest event in an event pair to the occurrence of the largest event. Also, the time interval in this time range is called transition time.

7) In minimum and maximum delay logic simulations, the time region in which the output states of a certain element are equal is called the regular time region of that element.

8) Irregular time domain refers to a time domain other than the regular time domain and the transition time domain of regular events.

FIG. 2 is a diagram showing the relationship between events and delay times using a buffer as an example. Figure 2(a) is a symbol diagram of the buffer,
Buffer 201 is provided with a minimum delay time and a maximum delay time, and they further have two delay times for the rise and fall of the output state of this logic element. In Fig. 2(a), this is rm! n+fm! n+γm
axt and fmax, and these are respectively called minimum rise delay time, minimum fall delay time, maximum rise delay time, and maximum fall delay time. FIG. 2(b) is a time chart showing the correspondence between the state change of the output bin OUT when an event pair is applied to the input bin IN of the buffer 201 and the above delay time. Event pair 210 is event 211 input to the minimum delay logic simulation and event 2 input to the maximum delay logic simulation.
12 years old. Both of these events indicate a rise from the logical value O to 1, and correspond to the regular event pair described above. By applying this event pair to the buffer 201, an event pair 220 is generated from the output pin OUT of the buffer 201. In the minimum delay logic shimmy range w7, event 221 occurs at the output pin OUT 7 m10 after event 211, and in the maximum delay logic simulation, event 222 occurs at the output pin OUT after event 212 by rmax. Event 240 generated by event pair 230 is due to fall time fmin + fmax. Also, in the time chart shown in FIG. 2(b), a time area 213 sandwiched between both events in each event pair,
223, 233, and 243 are the transition time ranges for these event pairs, and all other time ranges in FIG. 2(b) are regular.

Figure 3 shows the minimum delay logic simulation results (m
in) and the maximum logical simulation result (max)
This is a time chart. A method for determining the typical value of the logic state of each element in a logic circuit from the results obtained by minimum delay logic simulation and maximum logic simulation will be described with reference to FIG. min and m
Typical values are shown below ax. For the typical value in the regular time domain where the logical shimmy range results at min and max coincide, the state value based on the logical simulation result is used as the typical value. In this case, the logical state is said to be at a regular value. In addition, there are two state values T, which mainly represent the transition of logical states, and a state value C, which mainly represents the non-regular time domain due to the discrepancy between the two ring simulation results.
Define the state. Details of these two typical values T and C are shown in FIG.

FIG. 3(a) is similar to the change in the output state shown in FIG. 2. Each of time domains 311, 313, and 315 is regular. Typical values for this rounding are 0, 1, respectively.
It becomes 0. The transition time ranges for regular event pairs 301 and 302 each exist independently. In this case, the typical value is defined as T. In particular, the regular event pair 301 expresses the rising edge of a logical state, and the regular event pair 302 expresses the falling edge of a logical state, so they can be distinguished by giving R and F as typical values, respectively. However, in order to complicate the explanation, we will not distinguish between them below and assume that both have a typical value T.

Figure 3(b) shows a case where an irregular time region occurs due to the largest isolated event, and the isolated event 320
The typical value becomes C due to the occurrence of . FIG. 3C shows a case where an irregular time region occurs due to the minimum isolated event 330, and the typical value is expressed as C due to the occurrence of an isolated event 330. Especially in Fig. 3(b), the largest isolated event 3
20, even if event pair 321 exists before it, it is impossible for event pair 320 to occur in this transition time range, but the third
There is a possibility that the minimum isolated event in Figure (C) occurs in the transition time range of the event pair 331 that exists before it.

In this case, it is assumed that the typical value C is reached at the same time as the minimum isolated event occurs. The change in the typical value to C is due to the occurrence of an isolated event as described above. In addition, when an irregular event pair occurs from the regular time domain (for example, m1n
The typical value C also occurs at 0-+1, maxO-*X).

FIG. 3(d) shows a case where an irregular event pair 340 occurs during an irregular time domain having a typical value C. In this case, the typical value is left unchanged at C.

Further, a minimum isolated event 341 occurs, and the state in the figure changes to a regular state 343.

In FIG. 3(e), the minimum isolated event in FIG. 3(d) occurs during the transition time range of the irregular event pair, and in this case, the typical value 01 until the end of the transition time range 452. After that, it has a regular value of 353.

When the typical value changes from C to the regular value, Fig. 3(d),
In addition to the isolated events in Fig. 3(e), regular event pairs (for example, m1no−+1°ma
x X = 1), in which the typical value C moves to the typical value T due to a regular event pair and then changes to the regular value.

FIG. 3(f) shows a change in typical values when the transition time regions 361 and 362 of a regular event pair overlap. In a time domain 365, where the transition time domain in which the regular value in the time domain 363 first changes to the typical value T in the time domain 364 overlaps, the typical value is changed to the logical state according to the event pair that first appears. Time region 366 where the transition time regions no longer overlap
Now, let T be the typical value and return to the regular value in the time domain 367.

Fig. 4 is a time chart showing the calculation of typical values using a two-man power AND element as an example, Fig. 4 (a) is a symbol diagram of a two-man power AND element, and Fig. 4 (b) to Fig. 4 (f). is 2 man power A
This is an example of a change in the state of the output bin 0LIT when an event pair is input to the input bins N1 and IN2 of the ND element 401. In the input bin, m
The values of ln and max and their typical values are shown superimposed, and min, max, and typical values are shown separately in the output bin OUT.

Since this figure is only for illustrating the method of calculating typical values, all delay times of the AND elements are shown as 0. Even when delays are taken into account, there is no significant difference in the method of calculating the typical value.

FIG. 4(b) shows a case where there is no overlap in the transition time range of the input event pair of INI and IN2, the event pair 421 and 425 are not propagated to the output, and the input event pair 422 and 424 is transmitted to the tt output OUT. 4 events each
23 and 426, the state of propagation is shown.

FIG. 4(C) to FIG. 4(f) illustrate the case where the transition time ranges of input event pairs of input bins INI and IN2 overlap.

In FIG. 4(C), there is no essential difference from FIG. 4(b); event pairs 432 and 434 are not propagated to the output, event pair 431 is changed to event pair 433, and event pair 435 is changed to event pair 436. It is propagated to the output as is.

In FIG. 4(d), event pairs 441 and 442
does not propagate to the output, two event pairs 443 and 4
44 propagate to the output as event pairs 445 and 446, respectively, producing event pairs with overlapping transition times at the output as shown in FIG. 4(d).

FIG. 4(e) shows a case where one new event pair is generated from the two input event pairs. The minimum (min) event of the event pair 452 and the maximum ljl (max) event of the event pair 451 are propagated to the output bin OUT, and an event pair simply added to one input is propagated to the output as is. It's different from what you had. In this case, the event pairs in input bins IN1 and IN2 interact with each other to output event pair 45.
The same is true for the occurrence of event pair 456 by event pair 454 and 455, which are regarded as having caused event pair 454 and 455, but are not regarded as isolated events.

FIG. 4(f) shows a case in which an isolated event occurs; event pairs 461 and 462 are isolated on the minimum side (min), and event pairs 464 and 456 are isolated on the maximum side (max). An event occurs and irregular time zones 463 and 466 appear.

For the AND element, changes in the logical state of the output when an event pair is input have been exemplified above.

Similarly, multiple inputs and other logic elements (OR, INV).

For K (NAND, etc.), the typical value is calculated by defining the operation as described above.

FIG. 5 is a time chart for verifying the set-up time and hole time in an edge-type D-type F/F element, and shows the data line and The state change of the clock line CLK is shown based on regular events of the clock line CLK.The data to be latched by the D-type F/F element is given to the data line before the clock line CLK operates. Setup time is the minimum time interval that the clock line CLK can operate after data is prepared, and the minimum time interval that the clock line CLK can operate and provide the next data. is called hold time.

The relationship between the event pair 510 at the clock 1cLK and the event pair 520 at the data line shows how the setup time is verified.

No. 5 (b) for the specified set-up time.
4 for the time intervals 531, 532, 533, 534
Seed verification can be done on a regular basis. The time intervals 531, 532 or 533, 534 have the property of becoming shorter in order. Using this, it is possible to level the timing errors for each case determined to be inappropriate by verification, and it is possible to classify the errors. Verification is performed from time interval 531 to 534, and those that are found inappropriate by 531 are defined as level 1. Those that become inappropriate by 532 or 533 are defined as level 2. Those that become inappropriate by 534 are defined as level 3. Level 3 errors are then the most serious. The hold time can also be verified using the clock line CL.
It is possible to perform the same procedure, except that the time order of the K and data line event pairs is reversed. Note that the event pairs 521 and 52 in which the transition time range of the event pair on the data line overlaps the transition time range of the event pair on the clock line CLK
Each of the 3,524 cases results in the highest level of error in the setup and hold time verification. Also, if this timing verification is not performed at all, in the case of event pair 521.522, D type F/
The logic state of the output Q or Q of the F element 501 is a regular state, but the outputs 523 and 524 are irregular states. Therefore, by setting the case of event pair 521 and 522 to level 4 and the case of event pair 523 and 524 to level 5, it is possible to eliminate timing errors even in the early stages of design where timing has not been particularly rigorously verified. becomes possible.

FIG. 6(a) is a structural diagram of an event list constructed on a storage area on a computer when the present invention is applied to an event-driven logic simulation method. Reference numeral 610 is an area for storing pointers to event lists 620, 640, 660, etc. for the minimum delay logic simulation at each time and pointers to event lists 630, 650, 670, etc. for the maximum delay logic simulation. The structure of the basic unit 621 of the event list for the minimum delay logic simulation is shown at 622 in FIG. 6(b), and the structure of the basic unit 651 of the event list for the maximum delay logic simulation is shown at 652 in FIG. The basic units 622 and 652 are the link pointers for linking the basic units, the element number where the event occurred, its output pin number, the transition state caused by the event, and the logic simulation elements of the present invention. In order to control the event, the event type determines whether this event is an isolated event or forms a regular or irregular event pair, and if it forms an event pair, it has a pair event pointer to point to the other event of the pair. In particular, in the case of an event pair, the element number and output pin number of the two basic units connected by the pair event pointer are the same. In Fig. 6(a), element g is It is expressed for an event with a transition time range from time S to time U,
The transition time at this time is us. Figure 6 (a) middle 6
90 indicates the end of the event list.

FIG. 7 is a layout diagram of an example in which the structure of a logic circuit is constructed as a data structure on a storage area on an electronic computer. Element table 701 includes, for element numbers given by appropriate means to all elements of a logic circuit, an element type, a fan-in table pointer, and an output state table pointer for determining the operation of that logic element. The element type table 705 has pointers to the number of input bins, the number of output pins, and the truth or evaluation function that determines the logical operation of the element type.

The output state table 702 has an area for storing the output state of each output pin of each element.

It has a storage area for minimum delay logic simulation results, a storage area for maximum delay logic simulation results, and a storage area for typical values calculated from these. Furthermore, in addition to this, an area for storing four delay times given to the output pin, the fanout number of the output pin, and a pointer to the fanout table can be included.

The fan-in table 703 is for indicating which element's input pin is connected to which element's output pin. The output pin of each element is connected to the input pin of which element.

In the data structure, only the storage area storing the output state values of the output state table 702 is rewritten at each time by the logic simulation access means shown in FIG.
Other areas are provided by appropriate means before the start of the logic simulation.

〔Effect of the invention〕

As explained above, the present invention clearly handles the transition state of each element of a logic circuit by simultaneously performing minimum delay logic simulation and maximum delay simulation, and easily and accurately detects malfunction locations due to timing deviations. becomes possible. Particularly in verifying the set-up time and hold time of flip-flop elements, the verification results can be easily classified.

[Brief explanation of drawings]

FIG. 1 is a flowchart of the present invention, FIG. 2 is a relationship diagram showing the definitions of events in this method, minimum delay times rmin, fmin, and maximum delay times rmax fmax, and FIG. 3 is a diagram showing the minimum delay logic simulation (mi
n) and the maximum logical simulation (max). Fig. 4 is a time chart for calculating the typical value for an AND element using two people. Fig. 5 is for an edge type. A time chart for explaining setup time and hold time verification for a D-type F/F element, FIG. 6 is a structure diagram of an event list when the present invention is applied to an event-driven logic simulation, FIG. 7 is a layout diagram of an example of the data structure of a logic circuit constructed on an electronic computer. FIG. 8 is a 70-chart of a conventional logic simulation method. Agent Patent Attorney Susumu Uchihara J-Tsu 7j Xi Iχ Chiga! Figure 1. Kokukan Kanama Kaani Saotome dōdō b) (b) No. 10,000

Claims (1)

[Claims] In analyzing the logic operation in a logic circuit after gate-level logic design is completed, an electronic computer is used to collect information on the connection relationships of each element in the logic circuit and the minimum and maximum delay times, which are indicators of the operating speed of each element. logic simulation means configured as a data structure in the above storage area and simultaneously performs a logic simulation using the minimum delay time and a logic simulation using the maximum delay time based on test vector information applied to the logic circuit; and a typical value calculating means for calculating a typical value of each element in the logic circuit from two logic simulations, and calculating a logical operation for each element in the logic circuit from the typical value obtained from the typical value calculating means. A method for verifying the operation of a logic circuit characterized by analysis and analysis of its temporal operation.