JPH04105139A - Timing inspecting method - Google Patents

Abstract

PURPOSE:To attain the accurate timing inspection by transmitting the timing at each level and applying the date change processing to the timing of each level in accordance with the level of a data fetching clock. CONSTITUTION:The data signal and the clock set at an initialization part 30 are applied to a timing trace part 31, and the timing data on each level that undergone the timing trace through the part 31 is given to a timing check part 32. This part 32 includes a date change processing part 321 and a check part 322 and applies the data change processing to the worst timing data on each level received based on the tracing direction, the mode and the level. Thus a fact whether the set-up time conditions and the holding time conditions of a latch circuit can be satisfied or not. In such a way, the accurate timing inspection is attained with no interruption of a manual operation.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for verifying the timing of synchronously operating electronic circuits using multiphase clocks each having a different inherent level.

[Conventional technology]

When designing a semiconductor integrated circuit that includes a latch circuit and operates synchronously, timing verification is important. Timing verification is generally performed at the stage when the logic design is completed and at the stage when the layout for the logic design is completed. In the former, since the layout has not been completed, verification is performed using a virtual delay value based on the virtual wiring length, and in the latter, accurate verification is performed using an actual delay value based on the actual wiring length.

The reason why verification is performed in two stages is that if a timing problem is found after the layout is completed, it would take too much effort to correct it.

FIG. 5 is a block diagram showing the configuration of the circuit 15 to be verified.
A combinational circuit 17 such as an OR circuit is sandwiched between 6b and 6b. In the circuit 15, the data applied to the data signal line 18 is latched by the latch circuit 16a at the timing of the clock CI applied to the clock signal line 22, and the latch output S1 is applied to the combinational circuit 17 via the data signal line 19. The output S2 is latched via the data signal line 20 by the launch circuit 16b at the timing of the clock C2 applied to the lock signal line 23, and the latch output S3 is output to the data signal line 21.

Here, the characteristics of the signals propagating through each signal line will be explained below. The clocks C1 and C2 each have levels Tl and T2 (TI≠72) as information related to the input order including phase information, and their Ji1 periods are the same. Further, data signals St, S2 . S3 includes timing information such as timing tl, t2. t3, and levels Tl, TI, and T2 as information related to the input order.

Here, the level is an integer value defined for each clock, and indicates the order in which the clock is supplied within one cycle depending on the magnitude relationship of the value.For data signals, the level is the latch circuit that outputs it. corresponds to the level of the clock. Here, if the level is small, it indicates that the clock is supplied early.

Furthermore, the timing is a relative time measured from a reference time, and indicates the time at which the corresponding signal becomes stable or changes depending on the maximum or minimum delay mode, which will be described later.

Next, a conventional timing verification method for such a circuit will be explained.

FIG. 6 shows a timing chart of the operation of the circuit 15. When timing tracing is performed on the circuit 15, the data signal lines 18, 19, 20, 21 are considered as nodes, the latch circuits 16a, 16b, and the combinational circuit 17 are considered as nodes, and tracing is performed focusing on the nodes. Further, the timing trace includes a forward trace, a hackword trace, a maximum delay mode, and a minimum delay mode. Here, forward tracing refers to tracing performed in the direction along the actual signal flow (from the input side to the output side).

Bank word tracing, which is the opposite of this, is tracing performed in the opposite direction to the actual signal flow (from the output side to the input side). The reason for tracing in both directions during timing verification is to find as many timing errors as possible.

Maximum delay mode is a mode in which tracing is performed assuming the case where the propagation of a signal change is delayed to the maximum (the slowest (when it arrives)), and the worst timing is when the timing takes the maximum value. For example, check whether the launch circuit satisfies the sent-up time condition.The opposite minimum delay mode assumes that the propagation of the signal change is delayed to the minimum (the earliest arrival). In this mode, tracing is performed, and the worst timing is when the timing takes the minimum value. In this mode, for example, it is checked whether the hold time conditions of the latch circuit are satisfied. Also, the cent-up time is the time when the timing is input to the latch circuit. The hold time indicates how many seconds before the clock input to the latch circuit changes, if the signal state of the data signal is stable, the launch circuit will perform the specified launch operation. This is the time period that indicates how many seconds after the signal state of the data signal must remain stable for the latch circuit to perform the specified operation.

The forward trace and timing trace in maximum delay mode will be explained below.

The data signal S1 is input to the combinational circuit 17, and by adding the internal delay of the combinational circuit 17 to the timing t1, the data signal S1 is sent to the latch circuit 16b, which is the next node, at the timing E.
Timing trace is performed by propagating 2. Here, only one signal S1 is input to the combinational circuit 17, but since multiple signals are normally input to the node, the worst timing is selected according to the maximum or minimum delay mode. and adds internal delay to it.

As mentioned above, the timings tl, t2. t3 is expressed as a relative time from the falling edge of the clock C1 shown by the dashed line as a reference time, and the data signal S2 having the level Tl is taken by the launch circuit 16b into which the clock C2 having the lower level T2 is input. When input timing t1 of data signal S1 is input, clock C is calculated from value t2a obtained by simply adding the internal delay of combinational circuit 17 to input timing t1 of data signal S1.
A timing trace is performed using the value t2 obtained by subtracting the time of one clock from 2, and timing verification in the launch circuit 16b is performed. This is because all timing verification is performed from the reference time within one cycle, and in this case, since the value t2a exceeds the reference time of the next cycle, the value t2a exceeds the reference time of the next cycle.
2 to perform timing verification. and timing L
2 satisfies the cenotaph time of the launch circuit 16.

Generally, when capturing a data signal with a certain level using a clock with a different level, it depends on the direction of the trace (forward trace or hackword trace), the mode of the trace (maximum delay mode, minimum delay mode), and the level. A timing check is performed by adding or subtracting one clock from the timing of the data signal.

Hereinafter, the processing performed when the reference time is exceeded will be referred to as date change processing.

As shown in Figure 6, in the case of forward trace in the maximum delay mode, the data signal (S2) with a large level (T1)
When the data signal S2 is captured by the latch circuit 16b with a low level lock (C2) of the level (T2<Tl), the data signal S2 is captured at the clock after the next reference time, so the timing t2a simply added by the date change process is
Therefore, it becomes necessary to reduce the time of one clock. On the other hand, when data with a small level is imported using a lock with a large level (Tl<T2), the date change process is not necessary because the data is imported in one cycle.

Table 1 shows the relationship between the date change process and each of the above-mentioned modes.

Table 1 Here, "unnecessary" indicates that date change processing is unnecessary, "small-large" and "large-small" indicate the relationship between levels, and the symbol in front of the arrow indicates the level of the data to be propagated. Also, the part after the arrow indicates the clock level of the latch circuit that takes in the propagated data.

[Problem to be solved by the invention]

In the timing verification performed as described above, data signals having different levels may merge in a certain combinational circuit. Conventionally, when data signals of different levels merge, it is not known at which clock level the data signal output from the combinational circuit will be captured by the subsequent latch circuit, so it is unclear whether date change processing is necessary or not. It was not possible to select the worst timing of the data signal input to the circuit. That is, when a data signal having a level different from level T1 joins the data signal S1 having level T1 in addition to the data signal S1 having level T1 in the combinational circuit 17 of FIG. Since it was not clear whether date change processing was necessary or not, it was not clear which level of data would have the worst timing.

Therefore, in the past, the timing was manually specified for each level, and the timing was traced and checked using only the data signal at the specified timing, or the worst timing was determined by ignoring the level and using the magnitude relationship of the timing. However, the timing verification was incorrect.

The present invention was made in view of such circumstances, and by propagating the worst timing for each level to the propagation circuit,
To provide a timing verification method capable of performing accurate timing verification by performing necessary date change processing according to the level of a clock of a propagation circuit to be taken in even in an electronic circuit where data signals of different levels are merged. Make it a purpose.

[Means to solve the problem]

The timing verification method according to the present invention determines the worst timing for each level for data having different levels input to a combinational circuit when performing timing tracing, and provides the worst timing for each determined level to the propagation circuit. This is how it was done.

[Operation] In the present invention, when a plurality of data with different levels are inputted to the combinational circuit, the worst timing for each level is determined, and the worst timing for each determined level is given to the propagation circuit, and the timing verification is performed. Comparison of the trace direction, mode, and level of the data signal with the propagation circuit clock performs the necessary date changes and checks for accurate timing.

(Example) Hereinafter, the present invention will be described based on drawings showing examples thereof.

FIG. 1 is a block diagram showing the functional configuration of a timing verification device used to implement the timing verification method according to the present invention. In the figure, 30 is an initial setting section, which sets the level and timing of the data signal input to the input pin and the level of each clock in the forward mode, for example. The set data signal and clock are given to the timing trace section 31. The timing tracing unit 31 performs timing tracing, and calculates timing based on the timing data for each level determined by the level propagation unit 312, delay calculation unit 313, and worst case determination unit 314 to find the worst timing for each level. A timing calculation section 311 is provided.

The level propagation unit 312 adds level data to the worst timing data, and the delay calculation unit 313 adds line delay according to the timing trace. Also, the worst case decision section 3
14 calculates the worst timing of the output of each combinational circuit from the arrival time of the input and its internal delay. The timing data for each level traced by the timing trace section 31 is given to the timing check section 32. Timing check section 32
includes a date change processing section 321 and a check section 322,
Then, a date change process is performed on the worst timing data given for each level according to the trace direction, mode, and level, and it is checked whether the center up time condition and hold time condition of the launch circuit are satisfied from that number.

Next, the timing trace procedure of the present invention will be explained.

FIG. 2 is a diagram schematically showing a timing trace procedure in forward trace. In FIG. 2, 1 is an OR gate as a combinational circuit, and OR gate 1 has T
One input signal with I level is nT, tITI and t, respectively.
2T'...ttlT+". Also, there are two nT input signals with T2 level, each at t,
? 2. 12T2...t, input at the timing of 1□2T2. Based on a similar idea, m types of signals having different levels are input to the OR gate 1.

At this time, the data signal output from OR gate 1 is as follows:
Timing tTI with TI level, timing tT2 with T2 level..., timing tT- with Tm level, and one timing tTl for each of m levels.
, tTl...tT''' is propagated. The timing tT+ is the input timing t, TI, , with T level.
t, ..., the worst in TI=worst(t I"
+ t t”·t nr+”) plus the internal delay of OR gate 1.

Here -orst(t , T1. j tTl, ,
T...? +) is the maximum of input timings (,,TI,, t0a, 7) when in maximum delay mode, and conversely, when in minimum delay mode, input timing t,
TI, , t, lT, is the smallest among Tl.

When the signal propagates to the launch circuit 2, which is a propagation circuit, through the above processing, the launch circuit 2 adjusts the worst timing of the data signal according to the level of the clock that takes in the data and the level of the data signal output from the OR gate 1. Perform date change processing and check timing.

FIG. 3 is a flowchart showing the processing contents when timing is propagated at each gate by forward trace. First, check whether the verification is in the maximum delay mode (step #11), and if it is in the maximum delay mode, select one of the input signal levels (step #11). Find the timing with the value (step #12). This process is repeated until all levels are completed (step #13). Similarly, when in the minimum delay mode, find the timing with the minimum value of all levels of the input signal (step #14 ~
#16). After finding the timings for all levels, the worst case determining unit 314 determines the worst timing by adding the internal delay to the timing, and the level propagating unit 31
Level data is added to 2 and propagated to the next stage, 7,000 circuit 2 (step #17).

FIG. 4 is a flowchart showing the contents of timing check processing in the launch circuit 2. First, one of the levels of the input signal to the child circuit 2 is selected, and the level between that level and the clock is adjusted. Check whether date change processing is necessary considering the size, delay mode, trace direction, etc. (Step #21), and if date change processing is necessary as shown in Table 1, perform it (Step #22) , check the timing.

The timing check here is performed by checking the cent amplifier time condition of the latch circuit in the maximum delay mode, and checking the hold time condition of the latch in the minimum delay mode. Then, it is checked whether or not there are any unprocessed levels (step #24). If there are still unprocessed levels, the process returns to step #20 and the checks are continued until all levels have been checked.

Although the present embodiment has been described using an OR gate as an example of a combinational circuit, the present invention is not limited to this, and other gates and their combination circuits may be used.

Furthermore, in this embodiment, the internal delays are added after finding the worst timing of all levels, but this means that one level is selected, and when the worst timing is found, the internal delays are added, and the value is A similar effect can be obtained by holding it.

〔Effect of the invention〕

As explained above, according to the present invention, since the timing is propagated for each level, it is possible to perform date change processing according to the level of the clock that takes in data at the timing of each level. Even when taking in output from a circuit where signals with
An equivalent effect is achieved in which accurate timing verification can be performed without manual intervention.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the functional configuration of a timing verification device used to implement the timing verification method according to the present invention, FIG. 2 is a diagram showing a schematic processing procedure of timing trace, and FIG. Flowchart showing processing contents when propagating timing, No. 4
FIG. 5 is a flowchart showing the contents of timing check processing in a child circuit, FIG. 5 is a configuration diagram of a circuit to be verified in a conventional timing verification method, and FIG. 6 is a timing chart illustrating the operation of a launch circuit. 31... Timing trace section 312... Level propagation section 311... Timing calculation section 313...
Delay calculation unit 314...worst case determination unit Note that in the drawings, the same reference numerals indicate the same or equivalent parts. Agent: Yudai Oiwa]

Claims (1)

[Claims] (1) In a timing verification method of performing timing tracing to verify the operation timing of an electronic circuit including a combinational circuit that inputs a plurality of data having different levels related to the input order and a propagation circuit that takes in the output of the combinational circuit, the combination A timing verification method comprising determining the worst timing for each level for a plurality of data input to a circuit, and providing the determined timing for each level to the propagation circuit.