JPH02106961A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve the short channel-resistant effect characteristics of a P channel MOS type transistor by making the N-type impurity concentration of the source-drain regions and an N layer in a semiconductor layer in the lower section of the gate oxide film of the P channel MOS type transistor higher than that of an N layer in the lower section of the active base region of an N-P-N bipolar type transistor. CONSTITUTION:The N-type impurity concentration of the source-drain regions 17 and an N layer 10 in a semiconductor layer in the lower section of the gate oxide film 18 of a P channel MOS type transistor 3 is made higher than that of an N layer 9 in the lower section of the active base region 15 of an N-P-N bipolar type transistor 2. Phosphorus concentration is 3.0X10<16>(cm<-3>) or less in the N layer 9 and 3.0X10<16>(cm<-3>) or more in the N layer 10, thus acquiring breakdown strength between an emitter and a collector of 10V or more in the N-P-N bipolar type transistor, then allowing microstructure down to a gate length of 0.8mum or less in the P channel MOS type transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device using Bi-CMO5 (
Bipolar-Complementary-M
etal Oxide Sem1conductor)
Regarding type transistors.

[Conventional technology]

FIG. 1 is a sectional view of a main part for explaining structural examples of conventional and inventive Bi-CMO5 type O5 transistors.

In the figure, (1) is a P-type semiconductor substrate (hereinafter simply referred to as the substrate), (2), (3) and (4) are NPN bipolar transistor formation regions J formed on the substrate (1), respectively. P-channel MOS transistor (hereinafter referred to as
A formation region (simply referred to as P-MOS), an N-channel MOS transistor (hereinafter simply referred to as N-MO5) formation region,
(5) is a semiconductor epitaxial layer formed on substrate (1), (csa), (6b) and (6c) are substrate (
1) P+ formed by thermal diffusion after Ni ion implantation
The buried layers (7a) and (7b) are N layers formed by thermal diffusion after ion implantation into the substrate (1). (8a) and (8b) are semiconductor epitaxial layers (8a) and (8b).
5) P+ layer formed in (9), (10 is N layer formed in semiconductor epitaxial layer (5), aυ is 2 layers formed in semiconductor epitaxial layer (5), (2)
is an isolation insulating film for element isolation, (to) is the collector region of N), a◆ is the emitter region of N1, a5 is the P- type active base region, αQ is the P+ type external base region, αη is the P -Source/drain region of MO8, (T) is P -M
OS gate oxide film, Ql is P-MO5 gate electrode,
(7) is a side insulating film formed on the side of the gate electrode α of the P-MOS, υ is the source/drain region of the N-MO8, 4 is the gate oxide film of the N-MO3, and G11. ltN-
The MO5 gate electrode (c) is a side insulating film formed on the side of the N-MO5 gate electrode (2).

Conventionally, the N layer (9) and OQ were formed in the same process, so their N-type impurity concentrations were the same.

[Problem to be solved by the invention]

With the miniaturization of semiconductor devices, the gate length of P-channel MOS transistors has to be shortened.In order to obtain sufficient source-drain breakdown voltage and red voltage, it is necessary to shorten the gate length of P-channel MOS transistors. It is desirable to increase the impurity concentration. On the other hand, in an NPN bipolar transistor, in order to obtain a sufficient collector-emitter breakdown voltage, the N-type impurity concentration of the N layer (9) should be lower than that of the N layer αQ. This is desirable.

In the above conventional semiconductor device, the N layer (9) and the QO
Since the type impurity concentrations are equal, there is a problem in that it is not possible to set the N type impurity concentration such that the electrical characteristics of both the P channel MOS type transistor and the NPN bipolar type transistor are simultaneously optimized.

The present invention was made in order to solve the above-mentioned problems, and provides a semiconductor device formed on the same substrate, including a fine and high-performance P-channel MOS type transistor and an NPN bipolar type transistor. The purpose is to

[Means to solve the problem]

In order to solve the above problems, in the present invention, in a semiconductor device formed on a substrate including an NPN bipolar transistor and a P channel MOS transistor, the source/drain region and the gate of the P channel MOS transistor are N in the N layer in the semiconductor layer below the oxide film
The present invention is characterized in that the type impurity concentration is higher than the N type impurity concentration of the N layer below the active base region of the NPN bipolar transistor.

[Effect]

According to this invention, by increasing the N-type impurity concentration of the N layer αQ in the P-channel MOS transistor formation region, the short channel effect resistance characteristics are improved, while N m ( 9) N
By lowering the type impurity concentration compared to that of the N layer 00, a sufficient collector-emitter breakdown voltage can be obtained.

〔Example〕

A structural example of the Bi-CMO5 type O5 transistor of this invention is as follows:
The above conventional structure example is a semiconductor epitaxial layer (5)
The N-type impurity concentration of the N layer OQ formed in the N layer (9)
It is exactly the same except that it is higher than that of .

FIG. 2 is a sectional view of a main part for explaining a method of forming the N layer (9) and OQ in a structural example of a Bi-CMO3 type O3 transistor of the present invention.

In the figure, (1) to a are exactly the same as or equivalent to those shown in FIG. 1, (c) is an insulating film, and (26a)
.

(26b) and (26C) are ion-implanted P+ layers, (a)
is an insulating film, (c) is an ion-implanted N+ layer, (4) is an ion-implanted NJ layer, (to) is a photo-L/resist film (31a
) and (31b) are P layers obtained by thermally diffusing (26a) and (26b).

Hereinafter, the second method for forming the N layer (9) and aO will be explained.
The explanation will be given in order based on FIGS. 4 to 0.

Refer to FIG. 2-(c) A buried layer (6a), (
sb), (6C).

After forming (7a) and (7b), a silicon epitaxial layer (5) is grown.

Refer to Figure 2-(c) After thermally oxidizing the entire surface to form an oxide film (c) with a thickness of 100 to 1000, a nitride film (not shown) is
After forming and patterning a photoresist film (not shown) in areas other than the element isolation insulating film region and the N-channel MOS type transistor formation region, the nitride film is removed.

Next, implant boron at a surface concentration of I x 10” to lx
After forming ten ion-implanted P layers (26a), (26b), and (26c), the photoresist film was removed and a layer of 20cm thick was formed on the entire surface.
Form an oxide film with a thickness of 00 Å or more.

See Figure 2-〇 Phosphorus was implanted over the entire surface at a surface concentration of 3 x 10” (cm-
') After forming a photoresist film (2) only in the NPN bipolar transistor region and implanting phosphorus again, the surface concentration of only the P-MO5 formation region (3) is 3 x 1016 ( The ion-implanted N+Ra ridge and (2) are formed by adding ions so that the ion-implantation becomes more than low.

See Figure 2-〇 Loo, who removed the inside of the photoresist film.

Heat treatment is performed at ~1200″C to diffuse the implanted boron and phosphorus to form the N layer (9) and α0.P layer αυ,
(31a) and (31b) are formed.

FIG. 3 is a diagram showing measured data for explaining the phosphorus concentration of the N layer (9) and αQ and the electrical characteristics of the NPN bipolar transistor and the P channel MOS transistor of the present invention.

In the figure, the horizontal axis is the phosphorus concentration (X 10” (C!ll
-3)), and the vertical axis is the emitter-collector breakdown voltage ω of the NPN bipolar transistor and the critical gate length (μm) at which the P-channel MOS transistor causes punch-through due to the short channel effect.

By the method explained based on FIG. 2 above, the phosphorus concentration in the N layer (9) is set to 3. OX 1018 (am-") or less, while in the N layer αq it can be 3.OX 1016 (an-" or more), as shown in Figure 3, NPN
Bipolar transistors can be miniaturized to an emitter-collector breakdown voltage of 10 (V) or more, and P-channel MOS transistors can be miniaturized to a gate length of O, S (μm) or less.

〔effect〕

According to this invention, the short channel effect resistance characteristics of a P-channel MOS transistor are improved, and sufficient emitter-collector breakdown voltage is obtained in an NPN bipolar transistor, so that fine and high-performance devices can be fabricated on the same substrate. The present invention has the advantage that a semiconductor device including a P-channel MOS transistor and an NPN bipolar transistor can be provided.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a main part for explaining an embodiment of the present invention and a conventional example; FIG. 2 is a cross-sectional view of a main part showing an embodiment of the present invention in order of steps; The figure is a measurement diagram for explaining one embodiment of the present invention. In the figure, (1) is the substrate, (2) is the NPN bipolar transistor formation region, (3) is the P channel MOS transistor formation region, (5) is the semiconductor layer, (9 and a
QIt N layer, Q5 c active base region, (17) j,
tP-MOS (7) source/drain region, Q8j is P
-It is a gate oxide film of MOS.

Claims (1)

[Claims] (1) In a semiconductor device formed on the same substrate, including an NPN bipolar transistor and a P-channel MOS transistor, in the source/drain region of the P-channel MOS transistor and in the semiconductor layer below the gate oxide film. A semiconductor device characterized in that the N-type impurity concentration of the N layer is higher than the N-type impurity concentration of the N layer below the active base region of the NPN bipolar transistor.