JPH02123657U - - Google Patents
Info
- Publication number
- JPH02123657U JPH02123657U JP3063889U JP3063889U JPH02123657U JP H02123657 U JPH02123657 U JP H02123657U JP 3063889 U JP3063889 U JP 3063889U JP 3063889 U JP3063889 U JP 3063889U JP H02123657 U JPH02123657 U JP H02123657U
- Authority
- JP
- Japan
- Prior art keywords
- address
- eprom
- data
- wiring
- specific address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Microcomputers (AREA)
Description
図面は本考案のマイクロコンピユータを示すブ
ロツク図である。
３……ゲートアレイ、４……ＥＰＲＯＭ、６…
…マルチプレクサ、７……命令出力部、８……配
線指定ラツチ回路。
The drawing is a block diagram showing the microcomputer of the present invention. 3...Gate array, 4...EPROM, 6...
...Multiplexer, 7...Instruction output section, 8...Wiring specification latch circuit.
Claims (1)
配線指定データが特定アドレスに記憶されたＥＰ
ＲＯＭと、 イニシヤルリセツト時に発生する制御信号に基
づいて、前記ＥＰＲＯＭの特定アドレスをアクセ
スするアドレスアクセス手段と、 前記ＥＰＲＯＭの特定アドレスから読み出され
た前記配線指定データをラツチする配線指定ラツ
チ回路と、 前記イニシヤルリセツト時に発生する制御信号
に基づいて、前記ＥＰＲＯＭの特定アドレスから
読み出された前記配線指定データに拘らず、命令
出力が禁止される命令出力部とを備え、 前記イニシヤルリセツト時、前記配線指定ラツ
チ回路に保持された前記配線指定データによつて
、前記ゲートアレイを所定状態に配線することを
特徴としたマイクロコンピユータ。 (2) 前記アドレスアクセス手段は、 前記ＥＰＲＯＭの特定アドレスを示すアドレス
データを発生する第１のアドレスデータ発生部と
、 前記ＥＰＲＯＭの特定アドレスを除く所定アド
レスを示すアドレスデータを発生する第２のアド
レスデータ発生部と、 前記イニシヤルリセツト時に発生する制御信号
に基づいて、前記第１のアドレスデータ発生部か
ら得られるアドレスデータを選択出力するマルチ
プレクサと、 より成ることを特徴とする請求項(1)記載のマ
イクロコンピユータ。[Claims for Utility Model Registration] (1) In a microcomputer, a gate array and an EP in which wiring designation data for setting the gate array in a predetermined wiring state are stored at a specific address.
a ROM, an address access means for accessing a specific address of the EPROM based on a control signal generated at the time of initial reset, and a wiring designation latch circuit for latching the wiring designation data read from the specific address of the EPROM. and an instruction output section that is prohibited from outputting instructions based on a control signal generated at the time of the initial reset, regardless of the wiring designation data read from the specific address of the EPROM, . A microcomputer, wherein the gate array is wired in a predetermined state based on the wire designation data held in the wire designation latch circuit. (2) The address access means includes a first address data generating section that generates address data indicating a specific address of the EPROM, and a second address generating section that generates address data indicating a predetermined address other than the specific address of the EPROM. Claim (1) characterized in that it comprises: a data generation section; and a multiplexer that selectively outputs address data obtained from the first address data generation section based on a control signal generated at the time of the initial reset. The microcomputer described.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3063889U JPH02123657U (en) | 1989-03-16 | 1989-03-16 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3063889U JPH02123657U (en) | 1989-03-16 | 1989-03-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02123657U true JPH02123657U (en) | 1990-10-11 |
Family
ID=31255875
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3063889U Pending JPH02123657U (en) | 1989-03-16 | 1989-03-16 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02123657U (en) |
-
1989
- 1989-03-16 JP JP3063889U patent/JPH02123657U/ja active Pending
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