JPH02128251A - Drawing address operation system - Google Patents

Abstract

PURPOSE:To speed up a picture drawing speed by automatically operating an address which a picture memory access with a condition that a picture processing control part has set. CONSTITUTION:The picture processing control part 1 performs a drawing processing with respect to the picture memory 13, and a system consists of a read-only memory (ROM) storing the operation process of CPU, a peripheral logic circuit and the like in addition to CPU. When the picture processing control part 1 continuously access the picture memory 13 in vertical and horizontal directions, it automatically operates the address required for the access at every access only by performing the initial setting of the access address, the address space quantity of the horizontal direction and a control signal, and supplies it to the picture memory 13. Consequently, CPU does not need to operate the address whenever it accesses the picture memory 13. Thus, the picture processing can be performed at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a drawing address calculation method for an image processing device.
In particular, the present invention relates to a method for adding and subtracting drawing addresses during continuous reading and writing of image data to an image memory.

Conventionally, in this type of drawing address calculation method, a central processing unit (CPU) that performs image processing calculates a drawing address by a program and provides the drawing address to the image memory.

That is, since the drawing address calculation is performed every time the CPU accesses the image memory, a large amount of time is consumed in the address calculation by the CPU, resulting in a disadvantage that the image processing speed becomes extremely slow.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a drawing address calculation method that allows drawing addresses to be calculated at high speed.

Hokuho! According to the present invention, either an address located at an address between an image processing control circuit and an image memory and output from the image processing control circuit or a calculated address is supplied to the image memory. a first selector, an address holding means for holding the address given to the image memory, and an address space holding means for holding the horizontal address space amount of the image address space necessary for address calculation. a second selector that outputs either a value indicating the address space amount or a complement of the value; an adder that adds the input values; and a control signal output from the image processing control circuit. and an arithmetic type processing circuit that determines an arithmetic type, and an image processing control circuit that calculates an address to be accessed in the image memory under conditions set by the image processing control circuit.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in more detail with reference to the drawings showing one embodiment of the present invention.

Referring to FIG. 1, in one embodiment of the present invention, an image processing control unit 1 performs drawing processing on an image memory, and includes a read-only memory (ROM) that stores the operation process in addition to a CPU. Terminal A of the 0 image processing control section 1, which is composed of peripheral logic circuits and the like, is composed of a plurality of buses, and outputs an image address when accessing the image memory 13 and data to be set in the flip-flop 2. Terminal B outputs a latch signal for setting data output from terminal A to flip-flop 2.

Terminal C has a logical value of "1" when the image processing control unit 1 accesses the image address space in the horizontal direction, which will be explained later.
, is the output 41 of the first control signal which has a logical value of "0" when accessing in the vertical direction. Terminal 1 is an output terminal for a second control signal which takes a logic value of "0" when accessing the image address space in the direction of adding an address, and takes a logic value of "1" when accessing the address in the direction of subtraction.

Terminal E is a select switching signal terminal. When the logical value of the select switching signal is r□, the signal input to the terminal A3 of the selector 11 is output to the terminal c3, and when the logical value is 1j, the signal input to the terminal B3 of the selector 11 is output. is output to terminal c3. Terminal F is a terminal for a signal output when image processing control section 1 accesses image memory 13, and this signal is used for data latch of flip-flop 12.

The flip-flop 2 is connected to the terminal D1.
The information on the address data bus from the processing control unit 1 is latched by the signal input to the terminal CLKI, and the information is transferred to the terminal Q.
1 or output the inverted information to terminal 1.

The selector 3 is configured such that the logical value of the input data to the terminal E1 is "1".
”, the output logic value of terminal C1 is r□.

Fixed to. When the logical value of the input to the terminal E1 is "o" and the logical value of the input to the terminal 81 is r□, the terminal A1
The information input to the terminal c1 is output to the terminal c1, and when the logical value of the input to the terminal E1 is "o" and the logical value of the input to the terminal 81 is "1", the information input to the terminal 81 is output. is output to terminal c1.

The least significant bits of a plurality of binary information signals outputted from the terminal c1 of the selector 3 are individually input to the AND gate 4, and the two least significant bits from the terminal c1 of the selector 3 are inputted to the plurality of OR gates 5. All but the least significant bits of the digit information are input individually.

When the output of the AND gate 7 is a logical value r Input the complement to terminal A2 of adder 1°.

The NOT gates 6 and 9 and the AND gates 7 and 8 are operated by first and second control signals from terminals C and D of the image processing control section 1.

The adder 10 adds the binary information input to the terminals A1 and B2 and the logical value 'IJ or "0" input to the terminal C1, and outputs the result to the terminal 02.

When the logical value of the signal input to the terminal 83 is "0", the selector 11 transfers the information of the terminal A3 to the terminal 03 and outputs "1".
In this case, the information on the terminal 83 is outputted to the terminal 03, respectively.

The flip-flop 12 latches the information input to the terminal D2 when a signal is input to the terminal CLK2, and outputs the information to the terminal Q2.
Output to.

The image memory 13 is a memory for recording image information data, and when the image processing control section 1 accesses it, it inputs the drawing address to be accessed to the terminal A4.

Next, the operation of this embodiment will be explained with reference to FIGS. 2 and 3. When the image processing unit 1 accesses the image space on the image memory to which addresses are allocated as shown in FIG. 2 in the horizontal direction as shown by the arrow Set it to “0” and access from terminal A.
When the start address (address 1 in FIG. 2) is output and the image memory 13 is accessed, the address data is input to the terminal A3 of the selector 11 and output from the terminal C3, and is input to the terminal D2 of the flip-flop 12. is input. The signal output from terminal F during access is input to terminal CLK2 of flip-flop 12, the address input to terminal D2 is latched, output to terminal Q2, and the address (address 1) is input to terminal A4 of image memory 13. be done.

After that, when the image processing unit 1 accesses the image memory 13 by updating the address 2 and 3 continuously, the logic value of the first control signal of the terminal C is "1", and the logic value of the second control signal of the terminal C is set to "1". If the logic value of the signal "OJ" and the logic value of the select switching signal from terminal E is set to "1", the operation of each logic gate 4.5°6.7, 8.9 will cause the adder 1 to
The input logic value to terminal A1 of 0 is r□, the input logic value to one terminal C1 is [1], and since the value of the previous access address is input to terminal 82, from terminal 02 The output becomes "previous access address + 1", which is input to the terminal D2 of the 7-lip flop 12 through the terminal B3 and terminal C3 of the selector 11, and is latched when the image processing control section 1 accesses the image memory 13. Terminal Q2
and input to terminal A4 of the image memory 13. After that, when the image processing control unit 1 repeatedly accesses the image memory 13, the address is automatically updated by 11, and the second
Access is possible in the direction of the arrow ■ in the figure.

When performing an access as indicated by the arrow ■ in FIG. 2, first, the access start address is output from the end 4-A and the image memory 13 is accessed in the same way as in the case of the arrow ■. After that, the terminal C is set to the logic value "1", and the terminal R is set to the logic value "1".
”, when the image memory 13 is accessed with the logical value “1” at the terminal E, “1’s complement” is stored at the terminal A2 of the adder 10,
Since 'OJ' is input to the terminal C1 and the previous access start address is input to the terminal 82, the output from the terminal 02 becomes the access address j that is 1's complement ten ahead.

As a result, "previous access address -1" is output, and when the image memory 13 is accessed, the address with "-1" is supplied to the image memory 13, and subsequent accesses are automatically "-1". ” address is provided.

When addressing in the vertical direction as shown by the arrow ■ in FIG.
, and causes the flip-flop 12 to latch the access start address. Separately, the amount of horizontal address space in the image memory space (in Figure 2, the horizontal address ranges from 0 to 3, so it is 4) is set to the flip-flop 2.
Set it to .

After that, terminal C is set to logical value “0”, terminal D is set to “0”, terminal E is set to
When the logical value is "1", the horizontal address set in the flip-flop 2 is outputted from the terminal 01 of the selector 3 and inputted to the terminal A2 of the adder 10. Terminal 01 has a logical value of "0" and terminal 82 has the next access address, so the output of terminal 02 is "the access address 10 times ahead in the horizontal address space (in the example indicated by the arrow ■ in Figure 2)" , 4
14, address 8)'', and an address for performing a vertical access with increasing addresses as shown by the arrow ■ in FIG. 2 is automatically supplied to the image memory 13 each time it is accessed.

As shown by the arrow ■ in Figure 2, access in the vertical direction and in the direction in which the addresses decrease is similar to the direction of the arrow ■.
The drawing processing unit 1 sets the horizontal address space amount of the image memory space in the flip-flop 2, outputs an access start address from the terminal A, and accesses the image memory 13.

Next, set the terminal C to the logical value 'OJ, and set the terminal C to the logical value 'I
J, if child E is set to logical value "1", the complement of the set value output from terminal d1 of flip-flop 2 (
(inverted) is input to terminal A2 of adder 10. $-i
'-C1 is the logical value "0", terminal B2 is the previous access address, and the output value of terminal 03 is "previous access address - horizontal address space amount (B+4 in the example of arrow ■ in Figure 2) The complement of 7) becomes J, and the arrow in Figure 2 ■
The address for vertical access where the address value decreases as shown in is automatically transferred to image memory 1 each time it is accessed.
3.

FIG. 3 shows the relationship between the terminal states set in the image processing control circuit 1 and the circuit operations of this embodiment.

As explained above, according to the present invention, when the image processing processor successively accesses the image memory in the vertical or horizontal direction, the access address, the horizontal address space amount, the control By simply making the initial signal settings, the address required for each access is automatically calculated and supplied to the image memory, so the image processing unit no longer needs to calculate the address each time it is accessed.
In addition to being able to access the image memory at high speed, the program of the image processing unit can also be reduced in size.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram of an embodiment of the present invention, FIG. 2 is a diagram of an image address space on an image memory, and FIG. 3 is a circuit operation diagram. Explanation of symbols of main parts 1... Image processing control section 2.12... Flip-flop 3.11... Selector 4.7.8... AND gate 5. ...Multiple OR Gates 6.9...Knot Gates 10...Adder Applicant NEC Corporation (1 other person)

Claims (1)

[Claims] (1) a first selector located on an address between the image processing control circuit and the image memory and supplying either the address output from the image processing control circuit or the calculated address to the image memory; , an address holding means for holding an address given to the image memory, an address space amount holding means for holding a horizontal address space amount of the image address space necessary for address calculation, and the address space. a second selector that outputs either a value indicating a quantity or a complement of the value; an adder that adds input values; and an operation that determines an operation type from a control signal output from the image processing control circuit. a type processing circuit, and calculates an address to be accessed in the image memory under conditions set by the image processing control circuit.