JPH02128577U - - Google Patents

Description

[Brief explanation of drawings]

Fig. 1 is a diagram showing an example of the main part configuration of an LSI tester according to the present invention, Figs. 2 and 3 are time charts of signals of each part in Fig. 1, Fig. 4 is a diagram showing a conventional example, and Fig. 5 ~FIG. 7 is a diagram for explaining the problems of the conventional example. 1...VSG, 2...DUT, 10...VSM
, 13...ADC, 15...memory, 17...counter, 19...trigger circuit, 20...address/write pulse generator, 21...controller.

Claims (1)

[Claims for Utility Model Registration] Generated at the same time as a video signal is applied to an LSI with a chip television function (hereinafter simply referred to as DUT) in synchronization with a clock signal and the start position of the horizontal scanning line of the video signal. a video signal generator that outputs an event signal, an AD converter that captures the output signal of the DUT at the cycle of a clock signal and converts it into a digital signal, and a write signal that is applied from an address/write pulse generator that will be described later. a memory that stores the digital signal of the AD converter at the timing of , a controller that sets a set value N1 corresponding to the signal delay time Δt in the DUT to a counter described later, and a clock signal that is triggered by the occurrence of an event signal. A counter that outputs a signal S10 when the number of pulses of this clock signal reaches a set value N1 from the controller, and an address that applies a write signal and an address signal to the memory at the cycle of the clock signal using the generation of the counter output signal as a trigger.・LSI tester equipped with a light pulse generator and.