JPH02134843A - Integrated circuit - Google Patents

Abstract

PURPOSE:To obtain an integrated circuit which has a test pattern having a small number of pads and facilitating a stable test by a method wherein at least one of a plurality of probing terminals which are connected to the test pattern and, further, brought into contact with test probes is electrically con nected to a semiconductor substrate. CONSTITUTION:In an integrated circuit which has a test pattern 10 having fundamental elements for a test Such as transistors, resistors, via-holes 3 and wiring layers 4 in an active region formed on one main surface of a semiconduc tor substrate 5 and a plurality of probing terminals 1 connected to the test pattern 10 and brought into contact with the test pattern 10, at least one of the probing terminals 1 is electrically connected to the semiconductor substrate 5. For instance, one end of the via-hole test pattern 10 composed of the wiring metal layers 4 and the via-holes 3 is connected to the P<+>-type diffused layer 6 of the silicon substrate 5. In this case, if the characteristics of the test pattern 10 are to be tested, one probe is brought into contact with the pad 1 and the other electrode is connected to the rear of the silicon substrate 5.

Description

[Detailed description of the invention] [Industrial application field] TECHNICAL FIELD This invention relates to integrated circuits.

[Conventional technology]

Some integrated circuits have a test pattern consisting of basic elements for each test in order to monitor whether each element formed on a semiconductor substrate is formed as designed. .

In that case, it has a terminal that comes into contact with the needle of the probe so that the characteristics can be checked by an external tester.

FIG. 3 is a pattern diagram of an example of a conventional integrated circuit.

The integrated circuit pattern has a via hole inspection pattern 1o in which via holes 3 provided in a matrix are connected in series through a wiring metal layer 4, and pads 1 at both ends thereof.

[Problem to be solved by the invention]

The conventional integrated circuit described above has the following two drawbacks in the test pattern.

First, one test pattern requires at least two pads, so as the number of test patterns increases, the area of the pads also increases, increasing the chip size that forms the integrated circuit. In some cases, inspection patterns may be selected and stored due to chip size constraints.

Second, since each pad is inspected through the needle of the prober, there is a drawback that depending on the degree of contact between the needle and the pad, the inspection may be unstable.

An object of the present invention is to provide an integrated circuit having a test pattern with a small number of pads and which allows stable testing.

[Means to solve the problem]

The integrated circuit of the present invention includes a test pattern having basic test elements such as transistors, resistors, via holes, and wiring layers in an active region formed on one main surface of a semiconductor substrate, and a test pattern connected to the test pattern. The integrated circuit also has a plurality of measurement terminals for contacting a test probe, with at least one of the measurement terminals being electrically connected to the semiconductor substrate.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) and 1(b) are a pattern diagram of a first embodiment of the present invention and a sectional view taken along line AA' of a chip corresponding thereto.

In the method for manufacturing an integrated circuit, ions such as boron are first implanted into a part of the upper layer of a P-type silicon substrate 5, and then thermal diffusion is performed to form a P+ diffusion layer 6.

Next, a base insulating film 8 is formed on the surface, a contact hole 2 is opened corresponding to the P+ diffusion layer 6, and one side of the via hole inspection pattern 10 consisting of the wiring metal layer 4 and the via hole 3 is formed through the contact hole 2. is connected to the P+ diffusion layer 6 of the silicon substrate 5.

Thereafter, a glabellar insulating film 9 and a protective film 7 are formed.

The above explanation has exemplified the manufacturing process necessary to realize the inspection pattern of the present invention, but in reality, this pattern is realized by forming the pattern on a mask of an integrated circuit and performing the manufacturing process.

To check the characteristics of the via hole inspection pattern 10, one glove may be brought into contact with the pad 1, and the other electrode may be connected to the back surface of the P-type silicon substrate 5.

Therefore, the number of probes is reduced from the conventional two to one, and since the connection with the P-type silicon substrate 1 is stable, the problem of incorrect testing due to poor contact is reduced.

FIG. 2 is a pattern diagram of a second embodiment of the present invention.

The integrated circuit includes a via hole inspection pattern 10 a contact hole inspection pattern 11. Wiring layer inspection pattern 1
2. Resistance measurement pattern 13. It has an offset value measurement pattern 14 and a plurality of contact holes 2 and pads.

In this example, six test patterns are configured, and while the conventional technology required 12 pads, in this example, one of the patterns is all connected to the P-type silicon substrate through a hole to contact 1. Since they are connected, there is an effect that the number of pads is halved to 6.

In addition, by including the offset value measurement pattern 14 that is simply connected to the silicon substrate through the contact,
It is possible to know the contact resistance and the P-type silicon substrate resistance in advance.

For example, the true resistance value can be corrected by subtracting the measured value obtained from the offset value measuring pattern 14 from the measured value obtained using the resistance measuring pattern 13.

〔Effect of the invention〕

As explained above, the present invention connects one or more measurement terminals of the inspection pattern directly to the semiconductor substrate and uses the back surface as a pad for the measurement terminal, thereby making it possible to increase the pad area compared to the conventional inspection pattern. It can be made smaller by that amount.

Furthermore, since the measurement terminals can be removed from the back surface of the board, this method has the effect of allowing more stable testing than the method in which all the terminals are removed from probe needles.

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) are pattern diagrams of the first embodiment of the present invention and sectional views taken along line A to A' of the chip corresponding thereto;
FIG. 2 is a pattern diagram of a second embodiment of the present invention, and FIG. 3 is a pattern diagram of an example of a conventional integrated circuit. 1... Pad, 2... Contact hole, 3...
Via hole, 4... Wiring metal layer, 5... P-type silicon substrate, 10... Pattern for via hole inspection, 1
1... Contact hole inspection pattern, 12...
Pattern for wiring layer inspection, 13... Pattern for resistance measurement, 14... Pattern for offset value measurement. Agent Patent Attorney Shinkyo Uchihara

Claims (1)

[Claims] A test pattern having basic test elements such as transistors, resistors, via holes, and wiring layers in an active region formed on one main surface of a semiconductor substrate, and a test probe connected to the test pattern and in contact with a test probe. 1. An integrated circuit having a plurality of measurement terminals for controlling the semiconductor substrate, wherein at least one of the measurement terminals is electrically connected to the semiconductor substrate.