JPS6188539A - Mos field effect transistor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to an MO8 field effect transistor, an MO8 field effect transistor, and an MO8 field effect transistor in which the gate insulating film is particularly thinner than the external insulation film. .

Conventional technology MO8 field effect transistor (referred to as MO8-FET)
is a transistor element that is widely used from low frequency band to high frequency band, but especially in high frequency range, MO
811FETI/) surface frequency characteristics, such as gain, maximum operating frequency class, etc., are largely controlled by the MO8-FETcD parasitic valley vibration. Therefore, in order to improve the frequency characteristics of MO8@FJ&T, it is necessary to reduce the parasitic capacitance τ.

Fig. 3 1a) fi is a plan view of a conventional MOS-FET, PJE>[b), fc) are the same figure fa)
A-A and B-Bd; In the ii side view, 1 is one conductivity type, e.g. P- type, 2.3 is the opposite 4z type N+ drain and north gate, 4 is the gate insulating film, 5 ,6.7
are each gate.

The drain, source electrodes, and 8 are connected to an insulating film outside the gate insulating film.0 In order to reduce the parasitic capacitance of such a 1~■O8 FET, the gate, drain, and source electrodes 5, 6 are
．． It is better to make the insulating film under 7 thicker.

However, if the gate insulating film under the gate electrode is thick,
M for high frequency applications because the mutual conductance gm decreases.
OS-FET is designed to have several colors A. Therefore, as another means to reduce the parasitic capacitance of the MOS@FET, a method has been used to increase the thickness of the insulation under the drain and source electrodes as much as possible. However, when the difference in film thickness between the gate insulating film and the insulating film outside thereof becomes large, step-cutting occurs in the gate electrode at the step portion where the film thickness difference exists.

Problems to be Solved by the Invention In the wafer manufacturing process, it is impossible to detect if the electrode is about to break due to variations in the thickness of the insulator and electrode film within the wafer plane and from lot-1. M.O.S.
- The bias applied to the gate 1 pole of the FBT is approximately several volts in the operating state, but during the product assembly process, if a voltage is applied due to static electricity, etc., it will be affected. Therefore, in order to detect breakage, it is sufficient to apply a voltage, but this has the problem that even non-defective products are destroyed and cannot be detected.

20 Problems (il-Means for Solving the Problems) In order to solve the above problems, in the present invention, a check pattern r1 is formed on the pseudo gate electrode which is placed in the same step part as the gate electrode of the element part involved in the actual operation. By separately providing a check pattern and performing a destructive test using this check pattern, quality control of the p1 gate electrode step breakage is performed by simultaneously estimating the destructive strength of the element portion.

E, Example The present invention will now be explained by way of examples.

No. 1181(a) is a plan view of a check pattern according to an embodiment of the present invention, and FIG. 1181(b) is a plan view taken along line A-AM in FIG. Figure 1 (
a).

(In BL, in the same wafer, apart from the element part that actually operates, the external insulating film of the element part and the external insulation film 8 of the four balls are overlapped four times, and the thickness is similar to that of the gate insulating film of the element part. After the pseudo gate insulating film 14 is formed, a pseudo gate electrode 15 having a step 10 similar to the gate electrode of the element portion is provided over the pseudo gate insulating film and over the external insulating film 8.

When the probe 9 is applied to the upper part of the external insulating film 8 of the pseudo gate electrode 15 in such a check pattern and the voltage is increased, if there is no step break in the pseudo gate insulating film 14,
Dielectric breakdown of the pseudo gate insulating film 14 occurs at several tens of volts, and a short circuit current flows.

Unfortunately, if a break occurs in the pseudo gate insulating film 14.

A small current flows once, but no breakdown occurs and the circuit is in an open state.

FIG. 2(a) is a plan view of a check pattern according to another embodiment of the present invention, and FIG. 2(b) is a cross-sectional view taken along the line AA in FIG. Figure 2 fa), (b
), if this example is compared with the example shown in FIG. It differs from the example in FIG. 1 in that it extends across and over the external insulating films 8 on both sides, and the other parts are four-sided.

In the example shown in FIG. 1, it is impossible to detect if the break in the electrode is close to the breakdown voltage, but in this example, the two probes 9, 9 are placed on the external insulating film 8. If the gate electrode 16 is applied and a current is applied for 1 hour, the current will flow by the resistance of the electrode portion, but when the current reaches a certain value, it will become open. By looking at the current value distribution at this time, it is possible to detect a disconnection state. Therefore, this example is also effective in cases where electrodes cross over stepped portions of various companies, such as integrated circuits.

Effects of the invention MO8'&,! The J'F-effective transistor has a check pattern at the wafer stage or inside the chip as described above, so it is possible to create a step t1 in the element part that could not previously be detected during destructive testing. It can be estimated by inspecting the check pattern, making it possible to control quality in the wafer manufacturing process.

[Brief explanation of the drawing]

FIG. 1(a) is a plan view of a check pattern according to an embodiment of the present invention, FIG. 1(b) is a sectional view taken along line A-A in FIG. a) is a plan view of a check pattern according to the direction of implementation of the present invention;
A-Aljr surface view and contact probe wire diagram, Figure 3 fal
is a plan view of a conventional MOS field effect transistor, and (b) and (c) are the same [, 1 (al A-
A and BB sectional views. 1...P-base, 2, 3...Drain/source region, 4...Gate insulating film, 5...
...Gate box 1 pole, 6゜7...Drain...
Source electrode, 8...External insulating film, 9...
・Tip, 14...Next gate insulating film, 15°1
6...Pseudo gate electrode. Yo, Chi] 75. ＼、Representative patent attorney Hi Uchihara! -)ni,ノ(dol,)
C

Claims (1)

[Claims] The gate electrode has a step covering a gate insulating film that is thinner than an external insulating film by a step difference and extends over the external insulating film, and further includes a pseudo gate insulating film having a similar structure to the gate insulating film. A check pattern for step breakage measurement, which is provided on the pseudo gate insulating film and has a pseudo gate electrode having a step similar to that of the gate electrode, is provided within the same chip where the gate electrode is located or before it is divided into chips. A MOS field effect transistor comprising a MOS field effect transistor in a part of a wafer.