JPH02135533A - Fault processing system - Google Patents

Abstract

PURPOSE:To prevent the system down of the whole of an information processing system when a correctable error occurs frequently by detecting the frequent occurrence of the correctable error of a control storing circuit, and when it is judged that the error occurs frequently, separating an arithmetic processing unit from a system with a processor relief. CONSTITUTION:A trouble processor 1 executes the trouble information collecting processing and the trouble relieving processing at the time of occurring of the fault of other device including an arithmetic processing unit 2. A control storing circuit 3 is a memory to store the microprogram of the arithmetic processing unit 2 and has an error correcting code. An error counter 10 counts the number of times of occurrence of the correctable error of the arithmetic processing unit 2 in a constant time, when the number of times set beforehand is reached, a fault processor control part 7 controls to suppress the reception of an error occurrence report by an error suppressing circuit 9. Simultaneously, the instruction stopping interruption through a communicating part 11 to a fault processor 2 is generated to a microprogram control part 6 and switched to a normal fault processor. In such a way, even if the correctable error occurs frequently, the shutdown of the system can be eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a failure handling method, and more particularly to a failure handling method when correctable errors occur frequently in an arithmetic processing unit having an error-correctable control memory.

Conventionally, this type of information processing device has an error correction circuit in its control memory, so that when a correctable error occurs, it continues processing even if it occurs frequently. . Furthermore, when an error occurs, error information is collected by a service processor or the like, but this error information overflows due to frequent occurrence of correctable errors, so some devices suppress error acceptance.

In the conventional information processing device described above, even if a correctable error occurs in the control memory, the operation continues, so if a large number of correctable errors occur, the performance of the arithmetic processing device decreases. There is a drawback that it does. Also,
Because correctable errors occur frequently, if a correctable error turns into an uncorrectable error, the arithmetic processing unit will be unable to continue operating, and the information processing device will stop operating. There is.

In some cases, even a correctable error may cause a microprogram step in control storage to prevent instruction execution.

Therefore, the present invention was made to solve the drawbacks of the prior art, and its purpose is to prevent the entire information processing system from going down when correctable errors occur frequently. The object of the present invention is to provide a failure handling method that allows

According to the present invention, there is provided a failure handling method that collects failure information and performs failure relief processing when a failure occurs in an arithmetic processing device,
a counting means for counting the number of occurrences of a correctable error each time the arithmetic processing unit reports the occurrence of the correctable error; A suppression means for suppressing reception of an occurrence report and an interrupt means for generating an interrupt to the arithmetic processing unit when the number of occurrences has been reached are provided, and the contents of a software visible register in the arithmetic processing unit are frozen. According to the present invention, there is obtained a fault handling method characterized in that the contents of each of the registers are controlled to be transferred to a normal arithmetic processing unit.

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

In the figure, a failure processing device 1 performs failure information collection processing and failure relief processing when a failure occurs in other devices including an arithmetic processing device 2.

The control storage circuit 3 is a memory that stores a microprogram for the arithmetic processing unit 2, and also has an error correction code. The microprogram data read from the control storage circuit 3 is set in the microinstruction read register 5 to execute the command, but before that, the error correction circuit 4 checks the validity of the data, and if there is a correctable error, The corrected data is set in the microinstruction read register 5. At this time, error correction time F#
14 receives an error in the fault processing bag W1 and notifies the circuit 8 of the occurrence of an error.The circuit 8 receives the error.
Generates an interrupt. Note that acceptance of this error notification can be suppressed by the error suppression circuit 9.

The error counter 10 counts the number of error notifications accepted by the error reception circuit 8, and is reset at regular intervals. Therefore, this error counter 10 counts the number of times that a correctable error occurs in the arithmetic processing unit 2 within the certain period of time. When the count by the error counter 10 reaches a preset number of times, the failure processing device control unit 7 controls the error suppression circuit 9 to suppress acceptance of error occurrence reports. At the same time, an instruction stop interrupt to the arithmetic processing unit 2 is generated to the microprogram control unit 6 via the communication unit 11.

Next, the overall operation will be explained using the operation flowchart shown in FIG. When the failure processing device control unit 7 receives the error occurrence report described above, it updates the counter 10 and checks whether the counter exceeds a predetermined value N. If it is not over, the operation is continued as is.

Although the counter 10 is not shown in FIG. 2, it is assumed that the counter 10 is reset after a predetermined time has elapsed since the first error occurred. When the counter 10 exceeds N, the error suppression circuit 9 is set to temporarily suppress error acceptance.

Next, a check is made to see if there is any arithmetic processing device other than the arithmetic processing device 2, and if there is no arithmetic processing device, the operation continues. In this case, although not shown, the error suppression circuit 9 is released after a certain period of time has elapsed after being set, and error information is collected. This serves as a warning to maintainers, etc.

Next, a case where another arithmetic processing device exists will be explained. In this case, the arithmetic processing unit communication section 1
1 to notify the microprogram control unit of an instruction stop interrupt. The microprogram of the arithmetic processing unit 2 is executing a software instruction, and the failure handling device that received the response receives the division at the break of the instruction, suppresses execution of the next instruction, and returns a response to the failure handling device 1. 1 extracts the software visible register of the arithmetic processing unit 2 via the diagnostic interface and transfers it to another normal arithmetic processing unit (not shown). The subsequent processing is the operation of processor relief processing, which is a well-known technique, and will not be particularly explained here.

As explained above, according to the present invention, a frequent occurrence of correctable errors in a control memory circuit is detected, and when it is determined that a frequent occurrence of correctable errors occurs, arithmetic processing is performed using processor relief processing, which is a well-known technique. By making it possible to disconnect the device from the system, a large number of correctable errors in control memory can become uncorrectable errors, or instructions cannot be executed due to the microprogram step where the error occurs, and the system This has the effect of eliminating the need to stop operation.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a flow chart showing the operation of the blocks in FIG. Explanation of symbols of main parts 1...Fault processing unit 2...Arithmetic processing unit 4...Error correction circuit 5...Microinstruction read register 8...・・・
... Error reception circuit 9 ... Error suppression circuit 10 ... Error counter

Claims (1)

[Claims] (1) A fault handling method that collects fault information and performs fault relief processing when a fault occurs in an arithmetic processing unit, comprising a counting means that counts the number of occurrences of a correctable error every time the arithmetic processing unit reports the occurrence of a correctable error. , suppressing means for suppressing reception of the occurrence report of the correctable error when the counting number of the counting means reaches a predetermined number within a certain period of time; and an interrupt means for generating an interrupt, the contents of software visible registers in the arithmetic processing unit are frozen, and the contents of each of the registers are controlled to be transferred to another normal arithmetic processing unit. failure handling method.