JPH04293130A - Information processor - Google Patents

Abstract

PURPOSE:To decrease the correction of an ECC 1-bit error of a control storage part, and to realize the information processor having high reliability by providing doubly the control storage part. CONSTITUTION:Control storage parts 1, 2 are constituted of two of a first control storage part 1 and a second control storage part 2, and also, this processor is provided with a count register 8 for holding the count number of an ECC 1-bit error, when this ECC 1-bit error is detected from an ECC check circuit 6, an adder 9 for counting a value of the count register 8, and an overflow flip-flop 10 which is inverted at the time when the count register 8 overflows, and switches a first control storage part 1 and a second control storage part 2. In such a state, when the ECC 1-bit error is generated by the number of times exceeding a certain prescribed value, the control storage parts 1, 2 are switched, and the operation is executed by the control storage part having an actual result operated in a power turn-on state previously, and also, at the time of start, the ECC 1-bit error of the control storage parts 1, 2 is checked, and the operation is executed by the control storage part in which the ECC 1-bit error is small.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing device having a control storage section and controlling microinstructions, and in particular, to an information processing device having a control storage section and controlling microinstructions.
The present invention relates to an information processing device having a circuit that performs a check (Error Correcting Code) and corrects a control storage unit.

0002

2. Description of the Related Art Conventionally, this type of information processing apparatus has only one control storage section, and only has a circuit for correcting the control storage section every time an ECC 1-bit error occurs.

0003

[Problems to be Solved by the Invention] In the above-mentioned conventional information processing device, in a case where ECC 1-bit errors occur frequently, for example, in a case of a 1-bit fixed failure, the ECC
In order to perform a correction operation on the control storage unit for each 1-bit error,
The problem was that the execution of microinstructions was slow.

0004

[Means for Solving the Problems] An information processing device of the present invention includes an address register that stores the address of a control storage section that is currently being executed, a read register that stores the currently executed microinstruction, and a microinstruction that stores the currently executed microinstruction. an address generation circuit that generates an address in the control storage section of a microinstruction to be executed next from the address register and the read register; and an ECC check circuit that checks the read register. , an information processing apparatus comprising a correction circuit that corrects the contents of the read register and resets the contents in the control storage section when the ECC check circuit detects an ECC 1 bit error; When an ECC 1-bit error is detected by the ECC check circuit, there is a count register that holds the count of the ECC 1-bit error, and a count register that counts up the value of this count register. and an overflow flip-flop that inverts when the count register overflows and switches between the first control storage section and the second control storage section. Further, the information processing device according to another aspect of the present invention is provided with an auxiliary power supply that supplies power to the overflow flip-flop even in the power-off state, and which stores the control storage unit used before startup. It is designed to be used. Further, in the information processing device according to still another invention of the present invention, in the first invention, the number of ECC 1 bit errors in the control storage unit is counted at startup, and the number of ECC1 bit errors in the control storage unit is counted. E of
It is equipped with a compare circuit that compares counts of CC1 bit errors, checks ECC1 bit errors at startup, and uses a control storage section with fewer ECC1 bit errors.

[0005]

[Operation] In the present invention, when an ECC 1 bit error occurs a certain number of times or more, the control memory section is switched, and the control memory section is operated with a proven control memory section that has previously operated in the power-on state, and further, At startup, the ECC1 bit errors in the two control memory sections are checked and the control memory section with fewer ECC1 bit errors operates.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing an embodiment of the present invention. In this figure, 1 and 2 are control storage units that hold microinstructions, 3 is an address register that stores the address of the control storage unit that is currently being executed, and 4 is a read register that stores the currently executed microinstruction. , 5 is an address generation circuit that generates the address of the control storage section of the microinstruction to be executed from the address register 3 and read register 4, and 6 is an EC that checks the read register 4.
C check circuit, 7 is this ECC check circuit 6 is EC
When a C1 bit error is detected, a correction circuit corrects the contents of the read register 4 and re-sets it in the control storage section, and when a 1 bit error is detected by the ECC check circuit 6, a correction circuit 8 holds the count number of this ECC 1 bit error. A count register 9 is an adder that counts up the value of the count register 8; 10 is an overflow flip-flop that is inverted when the count register 8 overflows and switches between the control storage unit 1 and the control storage unit 2;
1 is an auxiliary power supply that supplies power to the overflow flip-flop 10 even in the power-off state, and 12 counts the number of ECC 1-bit errors in the control storage unit at startup, and calculates the number of ECC 1-bit errors in the control storage unit 1 and control storage unit 2. This is a compare circuit that compares counts.

By providing the auxiliary power supply 11, the system is configured to use the control storage section that was used before startup. Furthermore, by providing the compare circuit 12, the system is configured to check for ECC 1-bit errors at startup and to use a control storage section with fewer ECC 1-bit errors.

Next, the operation of the embodiment shown in FIG. 1 will be explained. First, the control storage section 1 holds microinstructions for controlling the information processing apparatus, and the address of the control storage section 1 is designated by the address generation circuit 5 from the address register 3 and the read register 4. Control storage 2 is the same as control storage 1 and also holds microinstructions. The address register 3 is the control storage unit 1 currently being executed.
Alternatively, the address of the control storage section 2 is stored, and the read register 4 stores the microinstruction currently being executed. The address generation circuit 5 generates the next address to be executed from the address register 3 and read register 4. E
When the CC check circuit 6 detects an ECC 1-bit error, it generates a set timing for the count register 8 and the overflow flip-flop 10, and the count number of the ECC 1-bit error is stored in the count register 8 by the adder 9.

Next, the operation of switching the control storage section when an ECC 1 bit error is detected will be explained. E.C.C.
Each time a 1-bit error is detected by the ECC check circuit 6, the adder 9 counts up the number of errors and stores the result in the count register 8. When the count register 8 counts up and the ECC 1 bit error exceeds a certain value, the overflow flip-flop 10 inverts the value it had so far. This overflow flip-flop 10 is used for switching between the control storage units 1 and 2. For example, when operating in the control storage unit 1, if an ECC 1 bit error of a certain value or more is detected,
The overflow flip-flop 10 switches to the control storage section 2 for operation. It also has an auxiliary power supply 11 for maintaining the state of the overflow flip-flop 10 even in the power-off state, and when the power is turned on, it operates using the control storage section that was previously operating in the power-on state. Also, at startup, the number of ECC1 bit errors in control storage unit 1 and control storage unit 2 is counted,
It has a compare circuit 12 for comparing the count number of ECC 1 bit errors, and the overflow flip-flop 10 is set to operate with the smaller control storage section.

0010

As described above, the information processing apparatus of the present invention switches the control storage section when an ECC 1 bit error occurs a certain number of times or more. In addition, it operates with a control storage unit that has a proven track record of previously operating in a power-on state. Also, at startup, the ECC1 bit errors in the two control storage units are checked and the control storage unit with fewer ECC1 bit errors operates. Therefore, the EC of the control storage section
This has the effect of reducing correction of C1 bit errors and realizing a highly reliable information processing device.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

[Explanation of symbols]

1, 2 Control storage unit 3 Address register 4 Read register 5 Address generation circuit 6 ECC check circuit 7 Correction circuit 8 Count register 9 Adder 10 Overflow flip-flop 11 Auxiliary power supply 12 Compare circuit

Claims (3)

[Claims] 1. An address register that stores an address of a control storage unit that is currently being executed, a read register that stores a currently executed microinstruction, the control storage unit that holds the microinstruction, and the address register. an address generation circuit that generates an address of the control storage section of the next microinstruction to be executed from the read register; an ECC check circuit that checks the read register; and an ECC check circuit that detects an ECC1 bit error. In the information processing device, the information processing device is provided with a correction circuit that corrects the contents of the read register and resets the contents in the control storage unit, wherein the control storage unit is composed of two control storage units, a first control storage unit and a second control storage unit. configured and said ECC
A count register that holds the count of the ECC 1 bit error when the check circuit detects the ECC 1 bit error, an adder that counts up the value of the count register, and an adder that inverts the value of the first ECC bit error when the count register overflows. a control storage section and the second
An information processing device comprising an overflow flip-flop for switching a control storage section. 2. The information processing apparatus according to claim 1, further comprising an auxiliary power source that supplies power to the overflow flip-flop even in a power-off state, and using a control storage unit that was used before startup. An information processing device characterized by: 3. The information processing apparatus according to claim 1, wherein the number of ECC 1 bit errors in the control storage section is counted at startup, and the number of ECC bit errors in the first control storage section and the second control storage section is counted.
Equipped with a compare circuit that compares the count of C1 bit errors, and checks ECC1 bit errors at startup.
An information processing device characterized in that a control storage unit with fewer CC1 bit errors is used.