JPH02137054A - Information processor - Google Patents

Information processor

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Publication number
JPH02137054A
JPH02137054A JP63290254A JP29025488A JPH02137054A JP H02137054 A JPH02137054 A JP H02137054A JP 63290254 A JP63290254 A JP 63290254A JP 29025488 A JP29025488 A JP 29025488A JP H02137054 A JPH02137054 A JP H02137054A
Authority
JP
Japan
Prior art keywords
cpu
emulation
memory
instruction
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63290254A
Other languages
Japanese (ja)
Inventor
Shinya Yuzawa
湯澤　真也
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63290254A priority Critical patent/JPH02137054A/en
Publication of JPH02137054A publication Critical patent/JPH02137054A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To reduce the load of an application executing CPU by separating an I/O emulation executing CPU and an I/O emulation program memory from the application executing CPU and a memory respectively. CONSTITUTION:The I/O instruction given from a 1st CPU 1 is detected by an I/O instruction detecting mechanism 5 connected via a system bus 3. Then a 2nd CPU 4 for I/O emulation is started if the I/O emulation is needed. The CPU 4 executes the emulation of the I/O instruction via an I/O emulation program stored in a 2nd memory 6 accessory to the CPU 4 and also controls the temporary stop of the CPU 1 as necessary via a CPU control mechanism 7. Thus it is possible to reduce the using frequency of the memory space of an application executing CPU as well as the load of the CPU.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、パーソナルコンピュータ等の情報処理装置に
関し、特に、入出力（Ｉ　１０）命令のエミュレーショ
ン方式に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing apparatus such as a personal computer, and particularly to an emulation system for input/output (I10) instructions.

〔従来の技術〕[Conventional technology]

従来、この種のＩ１０命令のエミュレーション方式は、
単一のプロセッサ（ＣＰ　Ｕ）上で純粋にソフトウェア
により実現されている。Conventionally, the emulation method for this type of I10 instruction is as follows:
It is implemented purely in software on a single processor (CPU).

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来のＩ１０命令のエミュレーション方式では
、単一ＣＰＵ上でソフトウェアにより実現するため、ソ
フトウェア格納のためのメモリ空間が必要であり、また
、単一ＣＰＵでの実行のため、処理効率が低下するとい
う欠点がある。In the conventional I10 instruction emulation method described above, since it is realized by software on a single CPU, memory space is required for storing the software, and processing efficiency decreases because it is executed on a single CPU. There is a drawback.

〔課題を解決するための手段〕[Means to solve the problem]

本発明による情報処理装置は、アプリケーション実行用
の第１のＣＰＵと、Ｉ１０命令エミュレーション実行用
の第２のＣＰＵとを別に有し、第１のＣＰＵからの特定
アドレスに対するＩ１０命令を検出する検出手段と、こ
の検出手段によって特定アドレスに対するＩ１０命令が
検出された時に、第２のＣＰＵから第１のＣＰＵの一時
停止を制御する制御手段とを何している。The information processing device according to the present invention separately includes a first CPU for executing an application and a second CPU for executing I10 instruction emulation, and detecting means for detecting an I10 instruction from the first CPU to a specific address. and a control means for controlling the temporary stop of the first CPU from the second CPU when the I10 instruction for a specific address is detected by the detection means.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図を参照すると、本発明の一実施例による情報処理
装置がブロック図により示されている。Referring to FIG. 1, an information processing apparatus according to an embodiment of the present invention is shown in a block diagram.

第１図において、１はアプリケーションソフトウェアが
実行される第１のＣＰＵ、２は第１のＣＰＵＩに付随す
る第１のメモリである。第１のＣＰＵＩからのＩ１０命
令は、システムバス３を介して接続されたＩ１０命令検
出機構５により検出され、Ｉ１０エミュレーンヨンが必
要な場合、Ｉ１０エミュレーション用の第２のＣＰＵ４
の起動を行う。In FIG. 1, 1 is a first CPU on which application software is executed, and 2 is a first memory attached to the first CPUI. The I10 instruction from the first CPUI is detected by the I10 instruction detection mechanism 5 connected via the system bus 3, and if I10 emulation is required, the I10 instruction is detected by the second CPU 4 for I10 emulation.
Start up.

第２のＣＰＵ４はそれに付随する第２のメモリ６」二に
あるＩ１０エミュレーションプログラムにより、Ｉ１０
命令のエミュレーションを実行し、必要に応じて、ＣＰ
　Ｕ　Ｉ１１御機構７を介して、第１のＣＰＵＩの一時
停止を制御する。The second CPU 4 is operated by the I10 emulation program in the second memory 6'2 associated therewith.
Execute emulation of instructions and, if necessary,
The suspension of the first CPU 1 is controlled via the UI 11 control mechanism 7.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明は、Ｉ１０エミュレーンヨ
ンを実行するＣＰＵ及びＩ１０エミュレーションプロダ
ラム用メモリを、アプリケーション実行用ＣＰＵ及びメ
モリより分離することで、アプリケーション実行用ＣＰ
Ｕのメモリ空間の使用やアプリケーション実行用ＣＰＵ
の負荷を軽減できるという効果かある。As explained above, the present invention separates the CPU for executing the I10 emulation program and the memory for the I10 emulation program from the CPU and memory for executing the application.
U memory space usage and CPU for application execution
This has the effect of reducing the load on people.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例による情報処理装置の構成を
示すブロック図である。 １・・・アプリケーションソフトウェアを実行するＣＰ
Ｕ、２・・・アプリケーションソフトウェアのためのメ
モリ、３・・・システムバス、４・・・Ｉ１０エミュレ
ーションを実行するＣＰＵ、５・・・Ｉ１０命令検出機
構、６・・・Ｉ１０エミュレーショングラムのためのメ
モリ、７・・・アブリグーンヨンソフトウェアを実行す
るＣＰＵの一時停止を制御する機構。FIG. 1 is a block diagram showing the configuration of an information processing apparatus according to an embodiment of the present invention. 1... CP that executes application software
U, 2...Memory for application software, 3...System bus, 4...CPU for executing I10 emulation, 5...I10 instruction detection mechanism, 6...For I10 emulation program Memory, 7... A mechanism that controls the temporary suspension of the CPU that executes the software.

Claims (1)

【特許請求の範囲】[Claims] １、アプリケーションソフトウェアが実行される第１の
プロセッサと、該第１のプロセッサ上で実行された特定
アドレスに対する入出力命令を検出する検出手段と、該
検出手段によって前記特定アドレスに対する入出力命令
が検出された時に、入出力命令エミュレーションを実行
するための第２のプロセッサと、該第２のプロセッサよ
り、前記第１のプロセッサの一時停止を制御する制御手
段とを有することを特徴とする情報処理装置。1. A first processor on which application software is executed, a detection means for detecting an input/output instruction to a specific address executed on the first processor, and an input/output instruction to the specific address detected by the detection means an information processing apparatus comprising: a second processor for executing input/output instruction emulation when the first processor is executed; and a control means for controlling temporary suspension of the first processor from the second processor. .
JP63290254A 1988-11-18 1988-11-18 Information processor Pending JPH02137054A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63290254A JPH02137054A (en) 1988-11-18 1988-11-18 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63290254A JPH02137054A (en) 1988-11-18 1988-11-18 Information processor

Publications (1)

Publication Number Publication Date
JPH02137054A true JPH02137054A (en) 1990-05-25

Family

ID=17753754

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63290254A Pending JPH02137054A (en) 1988-11-18 1988-11-18 Information processor

Country Status (1)

Country Link
JP (1) JPH02137054A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5307133B2 (en) * 2008-05-28 2013-10-02 パナソニック株式会社 Device emulation support apparatus, device emulation support method, device emulation support circuit, and information processing apparatus
CN107479979A (en) * 2017-08-31 2017-12-15 安徽江淮汽车集团股份有限公司 The cpu load rate optimization method and system of a kind of gear box control unit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5307133B2 (en) * 2008-05-28 2013-10-02 パナソニック株式会社 Device emulation support apparatus, device emulation support method, device emulation support circuit, and information processing apparatus
CN107479979A (en) * 2017-08-31 2017-12-15 安徽江淮汽车集团股份有限公司 The cpu load rate optimization method and system of a kind of gear box control unit

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