JPH02140010A - Low frequency band digital filter - Google Patents

Abstract

PURPOSE:To improve the accuracy of multiplication by applying multiplication in less bit number in which an effective digit number of a constant number below a decimal point is limited. CONSTITUTION:A delay data is generated by a delay element 29 in a unit time while being deviated by one address each for each arithmetic processing to one input data Xi, the data is multiplied with a stored and split constant, the result of arithmetic operation is obtained, a value delta is multiplied, and the input data Xi and data Xi-1+Yi-1 of two preceding sample are added to the result of multiplication. Moreover, a value of multiplying 2 with the data Xi-1+Yi-1 of one preceding sample is subtracted from the sum to calculate an output data Yi. Since the product sum is calculated by using constants a-e representing the effective digit sufficiently in 16 bits, the accuracy of the operation below the decimal point is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a low frequency band digital filter that processes time-series input data based on a predetermined algorithm and outputs the processed data as time-series data.

(b) Conventional technology In general, primitive information sources that exist around us, such as sounds and images, are often analog signals. A system that processes this analog signal using digital methods is Digital Signal 9I! , embedded equipment (digital signal,
Processing system: DSP system).

In recent years, the conversion of digital circuits to LSI has progressed rapidly, and it has become possible to easily implement a DSP system on a single chip.
Furthermore, compared to analog signal processing, D
SP systems have rapidly come into practical use. Further, the application range of DSP systems has expanded to include audio signal processing, communication signal processing, measurement signal processing, image signal processing, seismic wave signal processing, underwater acoustic signal processing, and the like.

In addition, in the audio field, CD (compact disc) players and DAT (digital audio
2. Description of the Related Art As the digital processing of audio signals such as in tape players progresses, DSP systems for digitally processing audio signals are being put into practical use.

A conventional DSP system has the architecture shown in FIG. 7 so that a digital filter can be easily formed.

In Figure 7, the data bus (1) includes an input/output circuit (
Ilo) (2), data RAM (2), multiplier (3),
Arithmetic circuit (ALU) (4), accumulator (ACC)
) (5), etc. are connected, and the output of data RAM (2) and the output of data ROM (6) are connected to a multiplier (3), and the multiplier '!'! J, the multiplication result output of the device (3) is A L U (
4) is applied to one input. Each of these circuits is controlled by a microcode signal output from a decoder (8) that decodes instructions sequentially read from the program ROM (7) in response to the instructions.

By the way, when realizing a graphic equalizer in audio signal processing, it can be obtained by cascading a plurality of stages of second-order direct type FIR filters as shown in FIG. The IIR type filter in Fig. 8 is 'I'1=CIXl+C! X, l-1+ CIxl-*
+C4Yl-1+ CsY+-t・・・・・・・・・
(1) This is a product-sum operation of the formula (C+, C!, Cs, C4, Cs are constants that determine the filter characteristics), and 2'' shown in (29)
' is a delay element of unit time (sampler period here), (30) is a multiplication element of constants C1 to C6, (31
-) is an addition element.

When realizing this digital filter with a DSP system, the calculation order of the nodes in the filter is determined, a program is created, and the program is stored in the program ROM (
7) and also store the constants of the calculation formula in the data ROM (6). Then, by executing the program, a product-sum operation is performed, and the operation result is stored in the data RAM.
(2) are stored sequentially.

(...) Problems to be Solved by the Invention The graphic equalizer function can be realized by cascading digital filters with different center frequencies in multiple stages, and in each stage, the product-sum operation of equation (1) is performed. ing.

However, in the case of a digital filter with a low frequency band with a center frequency of about 200 Hz, the significant digits below the decimal point of the constant for performing the sum-of-products operation are long, and when the sum-of-products operation is performed using a limited number of bits, for example, 16 bits, There were drawbacks such as deterioration of calculation accuracy, deterioration of filter characteristics, and distortion of audio signals in low frequencies.

In addition, in order to improve the calculation accuracy in the low frequency band, it is necessary to increase the number of bits of the constant and the number of focuses of the multiplier, which increases the size of the memory that stores the constant and the multiplier.
There is an inconvenience that becomes an obstacle when integrating the circuit.

(d) Means for solving the problems The present invention was created in view of the above points,
a plurality of first delay means for delaying digital data input in each predetermined time unit; and a constant determined for each of the input digital data and each delay output of the first delay means. a first multiplication means for multiplying;
a plurality of second delay means for delaying the output digital data in units of time; a second multiplication means for multiplying each delayed output of the second delay means by a predetermined constant;
a first addition means for adding each output of the multiplication means and each output of the second multiplication means; a third multiplication stage for multiplying the addition result of the first addition means by a constant; subtracting means for subtracting the output digital data from the digital data obtained, a third delay means for delaying the output of the subtraction means by the time unit, and a predetermined constant for a predetermined output of the third delay means. A fourth multiplication means for multiplication, the input digital data, the multiplication result of the third multiplication means, the multiplication result of the fourth multiplication means, and the output digital data of the third delay circuit are added together. A low frequency band digital filter is configured by the second adding means.

(4t) According to the means described in the operation description, a digital filter is realized (1
), the constants C,,C,,C,... in the low frequency band are α+β・δ [α is the integer closest to the constant, β is the difference between the integer a and the constant, and each constant divided by a common constant δ (δ divided by 1)], perform a product-sum operation of each constant β on the input data, then multiply by the constant δ, and calculate the multiplication result. It is possible to add and subtract each constant α and the result of the product-sum operation of the input data.

As a result, the decimal point of each constant is expressed as the product of a significant figure β and a very small common constant δ of 1 or less, such as β and δ, so β is a limited small number of bits,
For example, it is expressed in 16 bits, and it is possible to perform multiply-accumulate operations with data with high precision. Then, by multiplying the result of the product-sum calculation of β by δ, the calculation result of the part below the decimal point is obtained. On the other hand, by performing a product-sum operation on the integer part α and the data and adding both, the overall calculation result can be obtained, and calculations in the low frequency band can be performed with sufficient accuracy with a data length of 16 bits. obtain.

(F) Embodiment FIG. 1 is a circuit diagram of a low frequency band digital filter showing an embodiment of the present invention. In the figure, Z-I denoted by (29) is a delay element of unit time (sampling period M in this case), and can be constructed by a latch circuit or memory operated by a sampling signal. (30)
is a constant multiplication element, and (31) is an addition element, which is composed of a multiplication circuit and an addition circuit.

In the case of the conventional digital filter shown in Fig. 8, when the center frequency reaches a low frequency band of about 200Hz, the constant C
The number of effective digits from 1 to C3 cannot be represented by 16 bits. Therefore, in the present invention, each constant is α+β・
Convert to the form δ.

That is, α is the nearest integer to the constant, and β is the quotient of the difference between the integer α and the original constant C divided by a number δ smaller than 1. If the center frequency is 2001-1z, the constant 01~C,
C+ = 1 + a·δ C,=−2+b·δ C5=1+c·δ C,=2+d·δ ci=++−1+e·δ. Here, δ is 1/2" (integer is an integer).

Substituting these into equation (1), Y+=L-2L-++L-t+2Y+-+-Y+-f+
δ(aX, +bX+-++ CX+-x+dY+-++
eYl-s)=Xl-2(X+-+-'l'1-1)
+Xl-1-Y+-*+δ(aX+ bXl-+ +
CL-*+ dY+-1+eY+-*).

FIG. 1 shows a circuit that realizes this product-sum operation. That is, a
X+ + bL-+ + CL-s+ dY+-+ +
Find the calculation result of eYl-*, multiply it by δ, and add the input data island and the data X+- from 2 samplings ago to the multiplication result.
The output data Y is calculated by adding t-Y+-t, and then subtracting the product of the data X l-H-Y 1-1 from one sampling ago multiplied by 2 from the result. Therefore,
Constant a + b whose significant digits are sufficiently represented by 16 bits
Since the product-sum operation is performed using +C+d+e, the accuracy of calculations below the decimal point is improved.

FIG. 2 shows a circuit that implements a graphic equalizer. That is, the filters shown in FIGS. 1 and 8 are connected in cascade, and in the first stage, the input data is xl,
The constants are A, B, C, and D.

E, the output is yl, and in the second stage, the input data is yl
, constants a, b, Cv d+ e* δ, 2. The output data is 2. becomes.

The digital filter shown in FIGS. 1 and 2 is a DS
This can be realized by using program software using P.

FIG. 3 is a block diagram of an audio DSP that is convenient for implementing a digital filter, and includes a pair of digital processing circuits (9) and (10), and the digital processing circuit (9).
(10) Data bus (BUSI) (BUS2) (11
) and an interface circuit (12) connected to the data bus (11).
13), and a control circuit (14) that controls the operations of these digital processing circuits (9) and (10), a data input/output circuit (12), and an interface circuit (13).

The data bus (11) has a 24-bit configuration of 8 bits x 3 each. The data input/output circuit (12) receives 16-bit left channel and right channel sampling data (for example, in the case of a CD player, the sampling frequency is 44.1K data Iz) applied from the outside to the input terminal IN. Input 5 serially, send the left channel data to BUSI of the data bus (11), send the right channel data to BUS2 of the data bus (11), and further,
It receives and receives the processed left channel data sent to the data bus BUS1 and the processed right channel data sent out to the data bus BUS2L, and alternately outputs them serially from the output terminal OUT. The interface circuit (13) performs data transmission and reception between the DSP system and the microcomputer (not shown), and sends the constants of the digital filter applied from the microcomputer to the data bus (11), and , receives system status data, etc. sent to the data bus (11), and sends it to the microcomputer. The data processing circuit (9) is for processing data of the left channel, and the data processing circuit (10) is for processing data of the right channel, and each has exactly the same configuration. That is, the data processing circuits (9) and (10) include a data bus (11), data RAM (15), constant RAM (16), constant ROM (17), and address pointers (18) (19).
(20), multiplier (MUL) (21), A L U (
22), accumulator (ACC) (23), temporary register (TMPI, TMP2, ...)
(24). The data RAM (15) is a 24-bit x 128 memory that stores unprocessed data sent from the data input/output circuit (12) and data after arithmetic processing.
It is the first RAM with a capacity of
) and the input of the multiplier (21). constant RA
M (16) is 1 that stores constants such as coefficients of the digital filter sent from the interface circuit (13).
The second RAM has a capacity of 6 bits) x 256, and is connected to the data bus (11) and the other input of the multiplier 5 (21). The address pointer (18) is composed of 8 bits and specifies the address of the data RAM (15), and is controlled by the microcode INCl and DECI output from the control circuit (14), and the address data held therein is controlled by the microcode INCl and DECI output from the control circuit (14). It has the function of incrementing (+1) and decrementing (-1) the address data, and also has a built-in register that can set any value by a program and a circuit that compares the set value with the address data. When the result exceeds the set value, it becomes rQJ, and when the result of decrement becomes less than "0", it becomes the set value, that is, it has a function of cycling between "0" and the set value. This circular addressing function is used to simplify the product-sum operation of the digital filter. Also, the address pointer (19) is the constant R, A M (16)
This is a 10-bit pointer that specifies the address of the microcode INC2 output from the control circuit (14).
The function of incrementing the address data and the microcode C output from the control circuit (14)
It has the function of being cleared to "0" by LEAR2. Furthermore, the address pointer (20) is a constant ROM
(17) is an 8-bit pointer that specifies the address, and has a function of decrementing the address data by the microcode DEC3 output from the control circuit (14).

The multiplier (21) performs 24-bit x 16-bit multiplication, the 6 inputs are 24 bits, the B input is 16 bits, and the multiplication result is determined after one cycle. The six inputs and the B input of (21) are provided with input selection circuits MPXA and MPXB, and the input selection circuit MPXA is connected to the microcode A from the control circuit (14).
-BUS selects data bus (11), microcode A-DRAM selects data RAM (15) and applies it to six inputs, input selection circuit M P
The data bus (11
) and set the constant R by microcode B-CRAM.
AM (16) is selected, and constant ROM (17) is selected by the microcode B-CROM and applied to the B input. The multiplication result is output in 32 bits.

AL (22) is a 32-bit arithmetic circuit, which calculates the 32-bit multiplication result input to one side and the 32-bit multiplication result input to the other side.
Bit ACC (23) data is microcode A
Addition processing is performed using dd, and the result is converted to ACC(23
). Of the 32 focus points of ACC (23),
The upper 24 bits are connected to the data bus (11), and the lower 8 bits are connected to the lower 8 bits of the temporary register (24) by an auxiliary bus (25). The temporary register (24) is a 32-bit register TM.
Consists of PI, TMP2...TMP8, 32
This is a register that holds up to eight bits of data, and the upper 24 bits of each are connected to the data bus (11). The data bus (11) and the auxiliary bus (25) provide three connections between the temporary register (24) and the ACC (23).
2-bit data is transferred.

The control circuit (14) includes a program ROM (26) that stores programs, a program counter (PC) (27) that specifies the address of the program ROM (26),
The instruction decoder (1-DEC) (28) decodes the read instructions.

The program ROM (26) has a capacity of 32 bits x 512, and stores a program for realizing a digital filter and other necessary programs. The instruction decoder (28) decodes instructions and outputs microcode, and controls the address pointers (18), (19), and (20).
A-BUS, A-D that controls C2, DECI, CLEAR2゜DEC3, and input selection circuits MPXA and MPXB.
RAM, B-BtJS, B-CRAM, B-CROM,
Alternatively, it outputs ADD, THR, etc. that control the ALU (22).

This microcode includes data processing circuits (9) and (1), respectively.
Since the voltage is applied to a common circuit of each part of 0), the data processing circuits (9) and (10) are simultaneously controlled in the same way by executing two instructions.

FIG. 4 shows an example of instructions necessary to configure a digital filter in the DSP system shown in FIG. 3. In FIG. 4, the MUL instruction is a multiplication instruction that selects the objects input to input A and input B of the multiplier (21) and causes them to be multiplied. The AP instruction increments address pointers (18) (19) (20),
It is a decrement or a knoah. ALU
The command is a control command for ALU (22),
ADD converts the two input data into A L U (2
2), the addition result is held in ACC (23), ALUSUB subtracts the data of one input from the other input, and the result of subtraction is held in ACC (23), and ALUTHR is Nl calculation! This is an instruction to hold the multiplication result from (21) as is in ACC (23). R
AMID, TMPID, TMP2D, TMP3D
is a store instruction, which causes data on the data bus (11) to be stored in the data RAM (15) and temporary register (24). ACLS, TMPIS, TMP2S, TM
P3S is a transfer command, and is a command to send the data of the ACC (23) and temporary register (24) to the data bus (11) and the auxiliary bus (25).

Next, using the DSP system shown in FIG.
A method for realizing a graphic equalizer as shown in the figure will be explained.

FIG. 5 is a diagram showing a program for realizing the digital filter of FIG. 2, and FIG.
5), the layout of data stored in the constant RAM (16) and the temporary register (24) is shown in the figure. Multiplication of constants using the program in Figure 5 is C+B*
A + E + D + C+ b * a
+ e + d order constant RAM
Constants are stored in the same order from address "0" to address "19" in (16).

On the other hand, data RAM (15) contains Xl+Y
The data of l+Zl is written every 3 addresses, but the sampling period is, that is, for every operation process for one input data
i+1lZl. By writing 1, the delay element f-(
29) is created. Therefore, the second
In the case of the digital filter shown in the figure, the address pointer (18) has circular addressing from "o" to "7";
And, the address pointer (19) is set by the third program so that the addressing is circular from "0" to "9".
Set it.

Here, at the time when step "O" of the program in FIG. 5 is executed for input data X, data RA
When the contents of M (15) are as shown in FIG. 6(a) and the address pointers (18) and (19) are both address r
In the inputs A and B of 1), data R and AM (15) are stored at address "0".

Data x+-t (input data 2 samples ago) and constant R
The coefficient C stored at address "0" of A M (16) is applied, and the multiplication result is determined and output in the next step. Furthermore, at the end of step "0", address pointers (18) and (19) are both incremented by instructions API INC and AP21NC, and their contents become "1".

When step "l" is executed, similarly to step "O", data RAM (15) and constant RAM (16) are selected as inputs of the multiplier (21), and each address "
The data x1-1 stored in "1" and constant B are multiplier (2
1) is applied. Also, the result multiplied by the previous step "0" is the instruction A L U T HR Niyori, A
It passes through L U (22) and the first multiplication result C'X+-* is stored in 1: ACC (23). At the end of step "1", address pointers (18) and (19) are incremented by the instruction API INC, AP21NC, and their contents become address "2".

Next, when step "2" is executed, the instruction MULA-
BUS, B-CRAMi: data bus (11) at input A of multiplier (21), constant RAM at input B
(16) Ka! Choose. On the other hand, the contents of the temporary register TMP I are sent to the data bus (11) by the instruction TMP I S, and the data sent to the data bus (11) by the instruction RAMID is specified by the address pointer (18). The stored data is stored at address "2" of RAM (15). At this time, the temporary
Input data x1 externally applied to the data input circuit (12) every sampling period jυj is stored in the register TMP1 in advance. Therefore, input data x1
is multiplied by the constant A read from the constant RAM (16) by the multiplier (21), and the data RA
Stored at address "2" of M (15). On the other hand, by the instruction ALUADD, the multiplication result B' of C-x,-, stored in ACC (23) and step "l"
The addition of X+-+ is performed, resulting in B'X1-+ +
C-Xl-+ is stored in ACC (23).

The most of step “2”? Mugi, address pointer (18)
(19) is incremented, and its contents are the address “
3".

When step "3" is executed, inputs A and B of the multiplier (21) include the data RAM (15) and the constant RAλ1.
Data y1-8 and constant E stored at address "3" in (16) are applied, and the multiplication result A-x+ of step "2" and ACC (23) are applied by instruction ALUADD.
The content of B-X+-++C-X+-x is A L U (2
2), and the addition result is A-x++B-x+-
++C-X+-* is stored in ACC (23). At the end of step "3", address pointers (18) (19)
) is incremented and becomes address "4".

When step "4" is executed, data RAM (15) and constant RAM are input to inputs A and B of the multiplier (21).
The data Y+-+ stored at address "4" in (16) and the constant RI are applied, and the instruction ALUADD causes the multiplication result E-Y+-* of step "3" and ACC(
23) Contents A'X+-+ + B-X+-+ + C
'Xt-t is added in ALU (22), and the addition result is A-x++ B-X+-++C・x+-t+l”y+
-* is stored in ACC (23). Step "4"
At the end of ``, by command APIDEC, AP21NC,
The address pointer (18) is decremented to address r3J, and the address pointer (19) is incremented to address "5".

When step “5” is executed, 5F! Human power A and B of calculation u (21) include data yl stored at address "3" of data RAM (15) and constant RAM (1).
6) address r5. A constant C stored in is applied. That is, the multiplier (21) performs the second stage multiplication of the digital filter shown in FIG. 2 from step "5". On the other hand, according to the instruction ALUADD, the multiplication result D')'+-+ of step "4" and the contents A/X of ACC (23)
1+ B-++-++ c-xl-1+ E')'+-
t is added in ALU (22), and the addition result A-
x+ + B'X+-++C-X+-t+D-Y+-+
+E-'l+-t is stored in ACC (23).

At this time, the content of ACC(23) becomes the output y1 of the first stage digital filter. At the end of step "5", the address pointer (18) is incremented to address "4" and the address pointer (19) is incremented to address "6".

When step "6" is executed, the inputs A and B of the multiplier (21) are set to the address "
, 1'' and the constant RAM (1
6) is applied to the constant stored at address "6". Furthermore, the instruction ACOS causes data y; stored in the ACC (23) to be sent to the data bus (11), and the instruction TMP ID causes the data yl sent to the data bus (11) to be transferred to the temporary register TMP+. Stored in On the other hand, according to the instruction ALUTHR, the multiplication result C・y,−2 in step “5” is A, LU(22
) and is stored in ACC (23).

At the end of step "6", address pointer (1B) (1
9) is incremented to become address r5J and address "7J.

When step "7" is executed, the instruction MULA-BUS
, B-CRAM, the inputs A and B of the multiplier (21)
contains the data and constants sent to the data bus (11),
The constant a stored at address "7" of RAM (16) is applied. Also, instructions T~IPIS and RAM
The data y1 stored in the temporary register TMP1 according to the ID is sent to the data bus (11) and applied to the input A of the multiplier (21), and is also applied to the data RA specified by the address pointer (18). M (15
) is stored at address "5". On the other hand, the instruction ALU
By ADD, the multiplication result 11y+-1 of step "6" and C'y1-t of ACC (23) are A L U (22
) and the result is ')'y+-+10C・y
, -1 are stored in ACC (23). Step "
At the end of "7", address pointers (18) and (19) are incremented to address "6" and address "8".

When step "8" is executed, the address "6" of the data RAM (15) is input to the inputs A and B of the multiplier (21).
The data z1-8 stored in and the constant e stored at address "8" of constant RAM (16) are applied, while in ALU (22), the multiplication result a'y of step "7" is and data h stored in ACC (23)
'yl-++C-y+-t is added, resulting in a-y
I+b-y-1+C-y1-* is stored in ACC (23). At the end of step "8", the address pointers (18) and (19) are incremented, and the address pointer (18) (19) is incremented to
7” and the address becomes “9”.

When step "9" is executed, the address "7" of the data RAM (15) is stored in the multipliers A and B of the multiplier (21).
The data z1-5 stored in z1-5 and the constant d stored in address ``9'' of constant RAM (16) are marked on, while in ALT,' (22), step ``8''
The multiplication result e'Zl-1 and the data a-y++b-)'+-++C・yl-3 stored in A CC (23) are added, and the addition result 1-y++ FV'Jl-+ +
C'Y1-++ e-Zl-* is stored in ACC (22). When address pointers (18) and (19) are incremented at the end of step "9", both address pointers (18 and 19) become address rQJ.

When step "10" is executed, no multiplication is performed, and the multiplication results dz, -, and A CC (23
) Data stored in a-yl+ b-yt-H+
C'y+-t+e'Z+-t is added in A L U (22), and the addition result a-Y++ b-Y+-
++ Cf+-++ FZI-+ + eZ+-t is A
Stored in CC (23).

When step "ll" is executed, the data stored in ACC (23) is shifted to the right by n bits. The shifted result is δ(a-y++ b-yI-1+C
-yI-tod-Zl-++1"Zt-z). That is, since δ is set to 1/2", shifting n pits to the right means multiplying by 1/21.

When step "12" is executed, the instruction TMP3S transfers the data y+ -s -Z l-* held in the temporary register TMP3 to the data bus (11).
, and in A L U (22), A CC
It is added to the data in (23), and the addition result is Yl−*
-Zl-w+δ(a-y++b-Yl-++C-Y+-
m+clZ+-++(lZ+-t) is A CC(23)
is maintained.

When step "13" is executed, the instruction T M P2S
The data y+- of temporary register TMP2 is
+-Z+-t is sent to the data bus (11), and data y+-+'' is sent by instruction TMP3D to obtain delay data for the processing of the next sampling data.
-21-+ is written to the temporary register TMP3. On the other hand, the instruction ALUSUB causes ALU(2
2), the data held in the ACC (23) or the data sent from the data bus (11))'+-+
-Z+-+ is subtracted and the result is held in ACC (23).

When step "14" is executed, similarly to step "13", data y, -121-1 is sent to the data bus (11), and in ALU (22), ACC (
23) from the data held in yI-1-Z + -+
is subtracted and the result is written to ACC (23). The data of ACC(23) at this time is -2(yI
-+-2+-+)+ (Y 1- Goose-z + -!
) + δ (a“y++b°y+-1+ Coy
l-g +d-z, -++e-z+-t).

When step "15" is executed, the data x of the temporary register TMP 1 is sent to the data bus (11) by the instruction TMPIS, and added to the data of ACC (23) in the ALU (23). and the addition result is A
Written to CC (23). ACC at this time (
23) data is Yl-x (V+-+-Z+-+)
+(S'+-*-Zl-1)+δ(a-yl+b-y
l-r+c'Y+-@+d・z, -++e-Z+-t)
, that is, the output data Zi of the digital filter.

When step ``16J'' is executed, data z1 stored in ACC (23) is sent to the data bus (11) by instruction ACC8, and data z1 stored in ACC (23) by instruction RAMID is sent to data RAM (15) specified by address pointer (18). )
is stored at address "0".

When step "17" is executed, the instruction T M PIS
As a result, data yl of temporary register TMP 1
is sent to the data bus (11), and the data 2. is subtracted by A L tJ (22), and yI
-21 is stored in ACC (23).

When step "18" is executed, the instruction ACC8 sends the data Y+-21 stored in the ACC (23) to the data bus (11), and the instruction TMP2D sends the data Y+-21 stored in the data bus (11) to the data bus (11). Y+Zl is stored in the temporary register TMP2 and becomes delay data for processing the next sampling data.

At the end of step "18", the address pointer (18) is incremented to the address rlJ by the instruction APIINC. Therefore, the next sampling data
At the start of processing l+1, the data RAM (15) addressed by the address pointer (18) will be accessed from address "1" and will be shifted one address ahead of the previous start address.

By executing the program of steps "0" to "18" above every sampling period, input data X+,
Filter processing is performed on X+++I X++1..., and the contents of data RAM (15) are
It changes as shown in the figure (()(O)(...)(d)..., and the filter output Zl+z1 and to ZI+l+...
... is obtained.

In this way, the digital filter shown in FIG.
The product-sum operation of the low frequency band digital filter shown in the figure can be performed continuously, and the multiplication accuracy is improved because the effective number orders below the decimal point of the constant are represented by 16 bits.

(G) Effects of the Invention As described above, according to the present invention, in a low frequency band digital filter, the multiplication precision can be increased without increasing the number of bits for multiplication, so that the filter characteristics in the low frequency band can be improved. can be secured. Furthermore, it can be performed continuously with other low frequency band filter processing. In particular, when implementing a graphic equalizer using a DSP system, the number of program steps can be shortened, creating more room for other processing, which also contributes to improving the throughput of the entire DSP system.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing another embodiment, and FIG. 3 is a circuit diagram convenient for realizing the digital filter shown in FIGS. 1 and 2. A block diagram of the SP, FIG. 4 is a diagram showing an example of instructions used in the DSP device of FIG. 3, FIG. The data allocation of RAλ1, constant RAM, and temporary register is shown in the figure, FIG. 7 is a block diagram of a general SP device, and FIG. 8 is a circuit diagram of a conventional digital filter. (9)(10)...Digital processing circuit, (12)-
...Data input/output circuit, (13)...Interface circuit, (14)...Control circuit, (11)...
...Data bus, (15)...Data RAM,
(16)...Constant RAM, (17)...Constant RO
M, (18) (19) (20)...address pointer, (21)...multiplier, (22)...ALU
, (23)...accumulator (ACC),
(24)...Tembora no register, (25)...
Auxiliary bus, (26)...Program ROM, (2
7)...Program counter, (28)...Instruction decoder, (29)...Delay element,
(30)...Multiplication element, (31)...Addition element.

Claims (1)

[Claims] (1) a plurality of first delay means for delaying digital data input every predetermined time unit by the time unit; and a plurality of first delay means each delaying the input digital data and the delay output of the first delay means respectively. a plurality of second delay means for delaying the output digital data by the time unit; and a plurality of second delay means for multiplying each delayed output of the second delay means by a predetermined constant. a second multiplication means for adding each output of the first multiplication means and each output of the second multiplication means; and a first addition means for adding each output of the first multiplication means and each output of the second multiplication means; a third multiplication means for subtracting the output digital data from the input digital data; a third delay means for delaying the output of the subtraction means by the time unit; fourth multiplication means for multiplying a predetermined output of the delay means by a predetermined constant; and the input digital data, the multiplication result of the third multiplication means, the multiplication result of the fourth multiplication means, and the third A low frequency band digital filter comprising: second adding means for adding the output digital signals of the delay circuits of No. 3;