JPH02140964A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPH02140964A
JPH02140964A JP63295027A JP29502788A JPH02140964A JP H02140964 A JPH02140964 A JP H02140964A JP 63295027 A JP63295027 A JP 63295027A JP 29502788 A JP29502788 A JP 29502788A JP H02140964 A JPH02140964 A JP H02140964A
Authority
JP
Japan
Prior art keywords
pull
resistor
bonding
bonding pad
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63295027A
Other languages
Japanese (ja)
Other versions
JP2829994B2 (en
Inventor
Atsuhiro Hara
篤弘 原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63295027A priority Critical patent/JP2829994B2/en
Publication of JPH02140964A publication Critical patent/JPH02140964A/en
Application granted granted Critical
Publication of JP2829994B2 publication Critical patent/JP2829994B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/547—Dispositions of multiple bond wires
    • H10W72/5473—Dispositions of multiple bond wires multiple bond wires connected to a common bond pad
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To select in a bonding step and to shorten a time up to completion of a product by providing a first bonding pad with a pull-up resistor or a pull- down resistor and a second bonding pad for inputting or outputting a signal, and disposing the first and second pads in proximity. CONSTITUTION:A bonding pad 1-1 is connected to an inverter 1-2, a bonding pad 1-3 is connected to a pull-up resistor 1-4, and the pad 1-1 is connected to a lead frame 1-5 by a bonding wire 1-6. In order to contain the resistor 1-4, the pad 1-3 may be connected to the frame 1-5 by a bonding wire 1-7. In order to contain no resistor, the pad 1-3 may not connected to the frame 1-5 by the wire 1-7. Thus, it can be selected in a wire bonding step, and a time up to completion of a product can be shortened.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路に関し、特にプルアップ抵抗又
はプルダウン抵抗をオプションで外部導出端子に接続す
ることができる半導体集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit in which a pull-up resistor or a pull-down resistor can be optionally connected to an external lead-out terminal.

〔従来の技術〕[Conventional technology]

第３図と第４図に従来のプルアップ抵抗又はプルダウン
抵抗の内蔵を選択する一従来例を示す。FIGS. 3 and 4 show a conventional example in which a built-in pull-up resistor or pull-down resistor is selected.

第３図はプルアップ抵抗の内蔵を選択する回路図である
。第４図は第３図を実施するための簡単なレイアウト図
である。第４図においてボンディングパッド４−１は第
３図の端子３−１でありボンディングパッド４−１から
のびているアルミニウム配線４−２は第３図のインバー
タ３−２のゲートにつながっている。アルミ配線４−３
は、第３図のプルアップ抵抗３−３につながっている。FIG. 3 is a circuit diagram for selecting a built-in pull-up resistor. FIG. 4 is a simple layout diagram for implementing FIG. 3. In FIG. 4, bonding pad 4-1 is terminal 3-1 in FIG. 3, and aluminum wiring 4-2 extending from bonding pad 4-1 is connected to the gate of inverter 3-2 in FIG. 3. Aluminum wiring 4-3
is connected to the pull-up resistor 3-3 in FIG.

第３図において点線をつなぐことによってプルアップ抵
抗の内蔵を選択したことになり、これはデバイス的には
第４図において斜線部のアルミ配線４−４をつなぐこと
によりプルアップ抵抗の内蔵を選択したことになる。By connecting the dotted lines in Figure 3, you have selected a built-in pull-up resistor, and from a device perspective, by connecting the aluminum wiring 4-4 in the shaded area in Figure 4, you have selected a built-in pull-up resistor. That's what I did.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の半導体集積回路は拡散工程のアルミ配線
にてプルアップ抵抗又はプルダウン抵抗の内蔵を選択す
ることができるようになっているので、プルアップ抵抗
又はプルダウン抵抗の内蔵の選択を変更するたびにアル
ミマスクを作うナくてはならず、製品ができ上がるまで
時間が長くなるという欠点がある。In the conventional semiconductor integrated circuit described above, it is possible to select a built-in pull-up resistor or pull-down resistor in the aluminum wiring during the diffusion process, so each time the selection of built-in pull-up resistor or pull-down resistor is changed, The drawback is that it takes a long time to make the product, as it requires making an aluminum mask.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体集積回路は、プルアップ抵抗又はプルダ
ウン抵抗のついた第１のボンディングパッドを有してお
り、同パッドは信号入力用又は信号出力用の第２のボン
ディングパッドに近接して設けていることを特徴とする
。The semiconductor integrated circuit of the present invention has a first bonding pad provided with a pull-up resistor or a pull-down resistor, and the first bonding pad is provided close to a second bonding pad for signal input or signal output. It is characterized by the presence of

したがって、第２のパッドに接続されるべき外部リード
に第１のパッドもワイヤで接続すれば、プルアップ又は
プルダウン抵抗付の端子とすることができる。Therefore, if the first pad is also connected with a wire to the external lead to be connected to the second pad, it can be used as a terminal with a pull-up or pull-down resistor.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図は本発明の一実施例の構成図である。ボンディン
グパッド１−１はインバータ１−２につながっている。FIG. 1 is a block diagram of an embodiment of the present invention. Bonding pad 1-1 is connected to inverter 1-2.

ボンディングパッド１−３はプルアップ抵抗１−４につ
ながっている。ボンディングパッド１−１はリードフレ
ーム１−５とポンディングワイヤ１−６でつながってい
る。プルアップ抵抗１−４を内蔵する場合は、ボンディ
ングパッド１−３とリードフレーム１−５をポンディン
グワイヤ１−７でつなげばよい。内蔵しない場合は、ボ
ンディングパッド１−３とリードフレーム１−５をポン
ディングワイヤ１−７でつながないようにすればよい。Bonding pad 1-3 is connected to pull-up resistor 1-4. The bonding pad 1-1 is connected to the lead frame 1-5 by a bonding wire 1-6. When the pull-up resistor 1-4 is built in, the bonding pad 1-3 and the lead frame 1-5 may be connected with a bonding wire 1-7. When not built-in, the bonding pad 1-3 and the lead frame 1-5 may not be connected with the bonding wire 1-7.

ワイヤ１−７を設けるか否かは所謂ワイヤポンディング
工程で選択でき、製品完成を遅くすることはない。Whether or not to provide the wires 1-7 can be selected in the so-called wire bonding process, and the completion of the product will not be delayed.

第２図は本発明の他の実施例の構成図である。FIG. 2 is a block diagram of another embodiment of the present invention.

ボンディングパッド２−１．２−３．２−５とインバー
タ２−２、プルアップ抵抗２−４．２−８とは実施例１
と同じつながりになっている。さらにボンディングパッ
ド２−１とリードフレーム２−７とはポンディングワイ
ヤ２−８でつながっている。ボンディングパッド２−３
、又はボンディングパッド２−５もしくは両パッドをポ
ンディングワイヤ２−９又はポンディングワイヤ２−１
０でリードフレーム２−７につなげることにより抵抗値
の異なるプルアップ抵抗を内蔵することができる。Bonding pad 2-1.2-3.2-5, inverter 2-2, and pull-up resistor 2-4.2-8 are as in Example 1.
It has the same connection. Further, the bonding pad 2-1 and the lead frame 2-7 are connected by a bonding wire 2-8. Bonding pad 2-3
, or bonding pad 2-5 or both pads with bonding wire 2-9 or bonding wire 2-1
By connecting the lead frame 2-7 with 0, pull-up resistors with different resistance values can be built-in.

なお、上述した実施例に限定されず、プルダウン抵抗に
ついても同様に実施できる。また、パッド１−１．２−
１は入力端子に限らず、出力端子でも、入出力端子でも
よい。Note that the present invention is not limited to the above-mentioned embodiments, and may be implemented in the same manner with a pull-down resistor. Also, pad 1-1.2-
1 is not limited to an input terminal, but may be an output terminal or an input/output terminal.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明はプルアップ抵抗又はプルダ
ウン抵抗のついたボンディングパッドを設けることによ
りポンディング工程にてプルアップ抵抗又はプルダウン
抵抗の内蔵を選択することができ製品ができあがるまで
時間が短くできる効果がある。As explained above, in the present invention, by providing a bonding pad with a pull-up resistor or pull-down resistor, it is possible to select the built-in pull-up resistor or pull-down resistor in the bonding process, and the time until the product is completed can be shortened. effective.

１・・・・・・ボンディングパッド、１−２．２−２゜
３−２・・・・・・インバータ、１−４．２−４．２−
８．３−３・・・・・・プルアップ抵抗、ｌ−５，２−
７・・・・・・リードフレーム、１−６．１−７．２−
８．２−９．２−１０・・・・・・ポンディングワイヤ
、３−１・・・・・・端子、４−２．４−３・・・・・
・アルミ配線、４−４・・・・・・選択切り換えアルミ
配線。1...Bonding pad, 1-2.2-2゜3-2...Inverter, 1-4.2-4.2-
8.3-3...Pull-up resistor, l-5, 2-
7...Lead frame, 1-6.1-7.2-
8.2-9.2-10...Ponding wire, 3-1...Terminal, 4-2.4-3...
・Aluminum wiring, 4-4...Selectable aluminum wiring.

代理人　弁理士　　内　原　　　晋Agent Patent Attorney Susumu Uchihara

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例の構成図、第２図は本発明の
他の実施例の構成図、第３図は一従来例の回路図、第４
図は第３図の簡単なレイアウト図である。 １−１．１−３．２−１．２−３．２−５．４ＶＤＤ 第１ 図 筋２．図 第３図 、Ｆｒｄ図Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a block diagram of another embodiment of the present invention, Fig. 3 is a circuit diagram of a conventional example, and Fig. 4 is a block diagram of an embodiment of the present invention.
The figure is a simple layout diagram of FIG. 1-1.1-3.2-1.2-3.2-5.4VDD Figure 1 Line 2. Figure 3, Frd diagram

Claims (1)

【特許請求の範囲】[Claims] プルアップ抵抗又はプルダウン抵抗の内蔵を選択するこ
とができる半導体集積回路において、プルアップ抵抗又
はプルダウン抵抗のついた第１のボンディングパッドと
、信号入力用又は信号出力用の第２のボンディングパッ
ドとを有し、これら第１および第２のボンディングパッ
ドが近接配置されていることを特徴とする半導体集積回
路。In a semiconductor integrated circuit in which a built-in pull-up resistor or pull-down resistor can be selected, a first bonding pad with a pull-up resistor or pull-down resistor and a second bonding pad for signal input or signal output are provided. 1. A semiconductor integrated circuit comprising: a first bonding pad and a second bonding pad disposed close to each other.
JP63295027A 1988-11-21 1988-11-21 Semiconductor integrated circuit Expired - Lifetime JP2829994B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63295027A JP2829994B2 (en) 1988-11-21 1988-11-21 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63295027A JP2829994B2 (en) 1988-11-21 1988-11-21 Semiconductor integrated circuit

Publications (2)

Publication Number Publication Date
JPH02140964A true JPH02140964A (en) 1990-05-30
JP2829994B2 JP2829994B2 (en) 1998-12-02

Family

ID=17815376

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63295027A Expired - Lifetime JP2829994B2 (en) 1988-11-21 1988-11-21 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JP2829994B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10201710B4 (en) * 2001-01-18 2016-11-10 Fuji Electric Co., Ltd. A physical size semiconductor sensor having adjustment pads for digital adjustment of a sensor output signal and method of making the same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59188956A (en) * 1983-04-11 1984-10-26 Nec Corp Semiconductor device
JPS6122446A (en) * 1984-07-10 1986-01-31 Asahi Optical Co Ltd Actuator for two-dimensional drive of pickup for optical disc
JPS61173514A (en) * 1985-01-29 1986-08-05 Matsushita Electric Ind Co Ltd Signal processing circuit
JPS61224446A (en) * 1985-03-29 1986-10-06 Fujitsu Ltd Semiconductor integrated circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59188956A (en) * 1983-04-11 1984-10-26 Nec Corp Semiconductor device
JPS6122446A (en) * 1984-07-10 1986-01-31 Asahi Optical Co Ltd Actuator for two-dimensional drive of pickup for optical disc
JPS61173514A (en) * 1985-01-29 1986-08-05 Matsushita Electric Ind Co Ltd Signal processing circuit
JPS61224446A (en) * 1985-03-29 1986-10-06 Fujitsu Ltd Semiconductor integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10201710B4 (en) * 2001-01-18 2016-11-10 Fuji Electric Co., Ltd. A physical size semiconductor sensor having adjustment pads for digital adjustment of a sensor output signal and method of making the same

Also Published As

Publication number Publication date
JP2829994B2 (en) 1998-12-02

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