JPH02141122A - Delay circuit - Google Patents

Abstract

PURPOSE:To prevent the production of an erroneous output signal even if a PUT oscillation circuit is failed during time count by using an AND output signal between a self-hold output signal of a cathode side signal of a PUT being a component of a PUT oscillator and a selfhold output signal of a gate side signal as a retarded output signal. CONSTITUTION:Upon the reception of an input signal IN and an output signal S of a PUT oscillation circuit, a transistor(TR) Q2 is turned off and an arithmetic oscillator 2 is oscillated. The oscillated output signal is fed to a rectifier circuit comprising diodes D3, D4 and capacitors C1, C2,to obtain a DC output EDD. Even is a PUT oscillation output signal S is lost, the oscillator keeps the oscillation and held in itself till the input signal IN is lost. The PUT oscillator cannot be oscillated if a fault takes place in a component of the circuit. Thus, the occurrence of oscillation regardless of the absence of the input signal IN and the production of the rectified output EDD are avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a so-called on-delay circuit that generates an output signal after a predetermined time after receiving an input signal.

(Prior Art) Conventionally, an on-delay circuit has a configuration in which, for example, a counter is used, and after an input signal is input, a clock signal is generated, and this signal is counted to generate an output signal.

(Problem to be solved by the invention) However, in the method of using a counter, the counter may accidentally run out of control and an output signal is generated before the predetermined delay time has elapsed, or the circuit may malfunction and there is no input signal. There were cases where an output signal was generated. Particularly in controls where safety must be ensured, such errors can be dangerous.

(Means for Solving the Problems) In order to solve the above-mentioned conventional problems, in the delay circuit according to the present invention, an input signal is input to a delay circuit using a PUT oscillation circuit, and two of the oscillation circuits The two output signals are input to different fail-safe self-holding circuits, and the AND output signal of the two self-holding circuits is used as a delayed output signal.

(Function) According to the delay circuit of the present invention, it is possible to provide a fail-safe on-delay circuit that does not generate output signal power in the event of a failure.

(Example) Fig. 1 shows a basic circuit diagram for explaining the delay circuit according to the present invention, where Vcc is a power supply, l is a PUT (programmable unijunction transistor) oscillator, and 2 is an input signal IN and PUT. 2 is a time chart for explaining the operation of the basic circuit in which the AND operation with the output signal S at the cathode of PUT constituting the oscillator l is performed.

Next, the operation of the basic circuit shown in FIG. 1 will be explained with reference to the time chart shown in FIG.

A positive output pulse signal 5tpuT is generated from the cathode K to the terminal voltage of the resistor R.

Also, when the output signal S is generated, a gate voltage is generated.

The arithmetic oscillator 2 is a known fail-safe AND circuit,
Resistance R, R, R.

R,R,,R,R,R,. , R11, R and transistors Q, Q, Q, Q, Qs, forming an AND circuit using feedback oscillation.

That is, the human input signal IN and the output signal S of the PUT oscillation circuit
When the input signal is input, the transistor Q2, which was in a conductive state when there was no input signal, is turned off and oscillates in the next process.

Qt:OFF→Q, :OFF→Q+:ON→Qz:ON
→Q,: 0N-4Q,: OFF→Qz:OFF→・ This oscillation output signal is transmitted by transistors Q and Q.

and resistance R1! The DC output E
It becomes 0°. The output signal EDO generated by the feedback resistor RI
3, it is fed back to the input side of the PUT oscillation output signal S, so even if the PUT oscillation output signal S disappears, the operational oscillator continues to oscillate, and is self-held until the next input signal IN disappears. Ru.

In the circuit shown in the figure, the arithmetic oscillator cannot oscillate if any of the elements constituting the circuit fails, and therefore oscillates even though there is no input signal IN, producing a rectified output E. will not occur,
In addition, the PUT oscillation circuit cannot oscillate if a failure occurs in any of the elements that make up the circuit.Furthermore, if a short-circuit failure occurs in diode D1, the feedback voltage from resistor R+s is reduced by resistor R1, so the self-holding function is lost. Or, at least, if the diode D1, which does not generate the output signal Eeo in the absence of the PUT oscillation output signal S, has a disconnection failure, the signal S will not be input to the operational oscillator. However, if a short-circuit failure occurs between the gate G and the cathode of the PUT during time measurement, that is, while charging the capacitor C7, the output pulse S will be generated before a predetermined period of time has elapsed.

FIG. 3 shows an embodiment of a delay circuit according to the present invention, and the configuration shown in the figure does not cause the above drawbacks.

In the figure, the PUT oscillator 7, the operational oscillator 8.9, and the rectifier circuit 1O111 are composed of the same circuits as shown in the basic circuit of FIG. , rising edge dSo/di of signal S0
This is a time chart for (> O).

In FIG. 3, the operational oscillator 8 oscillates due to an erroneous output signal caused by a PUT failure of the PUT oscillator 7 or a disconnection failure of the resistor R0 during time measurement, and the output signal Ell (
Produces IA. However, at this time, since the negative pulse signal So of the PUT oscillator does not rise, the operational oscillator 9 cannot oscillate. The input signal S0 of the operational oscillator 9 is the human input signal I
It occurs once at the rising edge of N, but the signal S is sent to the calculation oscillator 8.
is not input, the arithmetic oscillator 9 does not oscillate.The 0th order signal S is generated, the arithmetic oscillator 8 oscillates, and the output signal E,
. 1 and then when a rising component of the signal S0 occurs, the operational oscillator 9 self-holds this signal dso/dt. Here, the arithmetic oscillator 8 has a function of self-holding the clock signal of the PUT oscillator, and the arithmetic oscillator 9 has a function of self-holding the normal operation signal of the PUT oscillator. Figure 3 logically shows that
The logic is such that the output signal of the AND of the self-holding output signal of the cathode side output signal of PUT (No. 8 and the self-holding output signal of the gate side output signal No. 1) is the delayed output.

Furthermore, the elements constituting FIG. 3 have a characteristic that they do not generate an output signal in the event of a failure, as explained in FIG. 1.

In addition, although the present invention was explained using the product name PUT, UJT (
It is clear that an oscillator circuit with a unijunction silane transistor or a double base diode (scientific name: double base diode) can be used.

(Effects of the Invention) As described above, since the AND output signal of the self-holding output signal of the cathode side signal of the PUT that constitutes the PUT oscillator and the self-holding output signal of the gate side signal is used as the delayed output signal, We were able to realize a structure that does not generate an erroneous output signal even if the PUT oscillation circuit fails.

[Brief explanation of the drawing]

FIG. 1 is a basic circuit diagram for explaining the present invention in detail, FIG. 2 is a time chart for explaining the operation of the basic circuit in FIG. 1, and FIG. 3 is an embodiment showing the configuration of the present invention. FIG. 4 is a time chart for explaining the operation of the embodiment shown in FIG. 7...PUT oscillator 8.9...Fail safe self-holding circuit Figure 2 ON FF (〉0)

Claims (1)

[Claims] A PUT (programmable unijunction transistor or double base diode) oscillation circuit 1, a fail-safe self-holding circuit 2 for self-holding the cathode side output signal of the PUT constituting the oscillation circuit 1, and the self-holding circuit 1. It consists of a fail-safe self-holding circuit 3 that self-holds the PUT gate signal of the oscillation circuit 1 that supplies an output signal to the circuit 2, and the logical product of the output signal of the self-holding circuit 2 and the self-holding circuit 3. A delay circuit characterized in that an output signal is a delayed output signal.