JPH02141996A - semiconductor storage device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

INDUSTRIAL APPLICATION FIELD 1 The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device incorporating a spare memory array, which has a function that enables testing of the spare memory array without cutting the fuse. This invention relates to a redundant circuit system suitable for improving relief efficiency. 2. Description of the Related Art Conventionally, a semiconductor memory device equipped with a test function for a spare memory array includes, for example, a system discussed in Japanese Patent Laid-Open No. 124299/1983. (Problem to be Solved by the Invention 1) In the above conventional technology, each unit redundant decoder circuit for selecting one spare row (column) is connected to an external terminal and an external terminal regardless of the information setting of the program element. A means for forcibly generating a relief decode enable signal using the input signal of There have been problems in that it is necessary to repeat tests and programs, resulting in poor repair efficiency, and it is not easy to detect defects that occur depending on the address scanning method.The purpose of the present invention is to solve the above problems. An object of the present invention is to provide a semiconductor memory device with a built-in redundant circuit that enables batch testing of all spare arrays using one external terminal.

[Means to solve the problem]

The above purpose is to provide a test signal generation circuit having one external terminal input that generates a redundancy test enable signal that is commonly input to all redundant decoders, and further activates a redundancy test enable signal for each unit redundancy decoder circuit by a relief decode enable signal. This is achieved by providing a relief decoder and a test decoder activated by a redundancy test enable signal, and selecting a spare row (column) only when either decoder is activated. [Effect 1] Each redundant decoder has a relief decoder and a test decoder that are independent of each other, and the test decoder is activated by a redundancy test enable signal generated by a test signal generation circuit that has one external terminal input. , it is also possible to test all spare arrays at once with one external terminal. Therefore, it is possible to repair the memory while avoiding defective locations in the spare array, and the repair efficiency and yield can be dramatically improved. [Example] Hereinafter, five examples of the present invention will be described using FIGS. 1 to 4. FIG. 1 shows a circuit configuration diagram of a first embodiment of the present invention. In the figure, 1 is a group of row (column) address input terminals, 2 is a group of address buffers that output pairs of complementary signals, and 3 is a group of address buffers that output pairs of complementary address signals.
A regular decoder circuit that generates m decode signals NR□ to NR for selecting one of the regular row (column) memory arrays 10, 4 is common to the test signal generation circuit 5 and other circuits 8 in the device. The input terminal T, 6 connected to is a unit redundant decoder circuit that outputs a decoded signal RR. 7 is a predetermined regular row (
column) prohibition signal ND that prohibits decoding to the memory array
9 is n spare row (column) memory arrays connected one-to-one to n (5m) redundant decoders; 11 is normal row (column) memory in which a defect exists; A program element connected to a pair of complementary addresses for setting the address of the array. 12 is a program element for activating a relief decode enable signal RDE when a defective address is set in the above program element group; 13 is a relief decoder for generating a relief decode signal RA; 14 is a relief decoder; A test decode signal TA represents a preliminary array test decoder that generates First, the operation of the redundant test signal generating circuit included in the redundant circuit will be explained with reference to FIGS. 2 and 3. FIG. 2 shows a circuit diagram of the redundant test signal generation circuit. The circuit in this figure consists of a predetermined number of diode-connected NMOS transistors each connected in series and a gate connected to a power supply Vc.
c is a supervoltage (power supply voltage VCC) consisting of an NMOS transistor whose source is connected to ground GND.
an NMOS for inputting the signal from the super voltage entry buffer to the gate and inverting the state of the flip-flop.
Consists of transistors and inverters. Here, the super voltage entry buffer is set to be activated only when a voltage higher than the power supply voltage by a predetermined voltage or more is applied to the input terminal. Further, the current driving ability of the NMOS transistor Q2 shown in the flip-flop is set to be smaller than that of the NMOS transistor Q2, and the current driving ability of the NMOS transistor Q3 is set to be larger than that of the NMOS transistor Q2. Therefore, as shown in the operational waveform diagram in Fig. 3, when the power is turned on, the nodes NT and NB in the flip-flop are set to 'H' (high potential) due to the unbalanced current drive capability.
, L" (low potential), and the output is set to 11 HII. In this state, even if a signal that operates within the power supply voltage range is applied to the input terminal, the supervoltage entry buffer is not activated and the output is is fixed at "H"', the chip performs normal operation unrelated to the output of this circuit.6 On the other hand, if a voltage higher than a predetermined voltage than the power supply voltage is applied to the input terminal in this state, supervoltage entry occurs. The buffer is activated, the flip-flop is inverted by Q3, the output becomes "L II", and a preliminary array test using this output becomes possible. In this case, it is not necessary to continue applying the supervoltage to the input terminal, but only for a period sufficient to invert the state of the flip-flop. Also, once this state is reached, the state of this circuit will not change even if a signal that operates within the power supply voltage range is applied to the input terminal, and if another circuit is connected to the input terminal, the signal that operates within the power supply voltage range will not change. Operation is possible. However, in this case, the other circuits must be inactive at "HII" or super voltage. In addition, in order to return from this state to the initial state, the power supply needs to be stepped down once. A schematic summary is shown in Figure 3. As shown in the figure, the circuit of this embodiment has a built-in redundant test signal generation circuit, so that the signal applied to the input terminal operates within the power supply voltage range. In the case of normal operation, only other circuits in the chip operate, and the preliminary array test decode enable signal RTE is not activated and is fixed at lHI''. Furthermore, if we assume a normal operating state before setting predetermined information to the program element in the redundant decoder by a method such as cutting a fuse in order to repair a defect in the regular memory array, the repair decode enable signal and the =
1 to n) are also not activated and are fixed to 11 HII, so the redundant decode output signal RRi (x = 1 to n) and the normal decoding inhibition signal NDI are fixed to "L", and the normal decoder 3 using the normal address signal A predetermined regular array 10 is selected according to the method. In this case, the redundant circuit has no effect on the selection of the regular array. Once a supervoltage is applied to the input terminal T in this state, the circuit enters a preliminary array test state as shown in FIG. That is, the output RT of the test signal generation circuit
E is fixed at ``L'' and a test decoder that selects a spare row (column) array for testing is activated. Since the test decode signal T
A+, (i = 1 to n) and redundant decode signal R
R, (i=1 to n) is generated. In this case, RDE Yu(
Since i=1 to n) are not activated and are fixed to "H", RA is fixed to 11 L II and has no effect on test decoding. Also, when the predetermined RR, becomes (l HII), the signal ND also becomes II H11, prohibiting decoding of the regular array. Which TA, (
If none of the spare row (column) arrays (i=1 to n) are activated, no spare row (column) array is selected and a predetermined regular row (column) array is selected according to the address in that case. In this state, all spare row (column) arrays can be tested to detect internal defects. FIG. 4 schematically shows operational waveforms when a transition is made from the normal operation to the backup array test mode, and one backup array, a regular array, and another backup array are sequentially selected. If a defect exists in the regular memory array, select the spare row (column) array in which the defect detected in the above state exists. Set the array address and relief decode enable flag off-chip. In this case, the rescue decoder in the predetermined redundant decoder is activated, the predetermined RA signal becomes 11 HII,
RR, is set to ``H'' to select a predetermined spare row (column) array that does not contain a defect, and also prohibits selection of a predetermined normal row (column) array that includes a defect by NDI, and to The test decoder in the redundant decoder is deactivated and selection of the redundant decoder during testing is prohibited. Basically there is no need to perform a preliminary array test at this point, but if such a need arises, In order to deal with this, the above measures are taken.In addition, in such a case, in order to avoid multiple selections during testing, the address of the bit set in the program element of a given redundant decoder and the test decoder of other redundant decoders are It is necessary to set the program so that the address of the S bit connected to the S bit does not match in the S bit part.According to this embodiment, one terminal that can be shared with the input terminal to other circuits in the chip By simply providing external terminals, it is possible to test all spare arrays at once, making it possible to detect defects that occur depending on the address scanning method, and it is expected that a relatively large-scale spare array will be required. In a large-scale semiconductor memory device, it becomes possible to efficiently detect defects in the spare array and repair the memory by avoiding them, which has the effect of dramatically improving repair efficiency and yield. According to the authors, a resilient method of applying a supervoltage to the input terminal has the effect of realizing a preliminary array test mode, and since the period of supervoltage application is extremely short, it can be used for long-term testing. There is also the advantage that there is almost no problem with reliability, and the supervoltage generation circuit required for testing can be easily realized.In addition, in the above embodiment, the method uses the address buffer output as the input of the redundant decoder. Although this embodiment has been explained using an example, it is natural that this embodiment can also be applied to a method using a predecoder output that prezo-codes an address.
Although the description has been made using a NOR gate as the logic gate, it goes without saying that a similar circuit can be constructed using a NAND gate. Further, the above embodiment is applicable to both row and column redundancy in a semiconductor memory device. (Effect of the invention 1) According to the present invention, it is possible to test all spare arrays at once by simply providing one external terminal that can be shared with input terminals to other circuits within the chip. To efficiently detect and avoid defects in a spare array in a large-scale semiconductor memory device that is capable of detecting defects that occur and is expected to require a relatively large-scale spare array, and to rescue memory by avoiding the defects. This has the effect of dramatically improving relief efficiency and yield.According to the present invention, a preliminary array test mode can be realized by applying a supervoltage to the input terminal, which has recovery properties. In addition, since the period during which supervoltage is applied is extremely short, there are almost no problems with long-term reliability, and the supervoltage generation circuit required for testing can be easily realized. In addition, since the area required to form the program element occupies a considerable portion of the redundant circuit, the increase in the occupied area for realizing the present invention is small and can be realized with a relatively small occupied area. There is.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention, FIG.
FIG. 3 is a circuit configuration diagram and an operation waveform diagram of a test signal generation circuit built in the first embodiment. FIG. 4 is an operation waveform diagram when the normal operation mode is shifted to the preliminary array test mode in the first embodiment. Explanation of symbols 1... Address input terminal, 2... Address buffer, 3... Regular address decoder, 4... Input terminal,
5... Test signal generation circuit, 6... Unit redundant decoder, 7... Regular decoding inhibit circuit, 9... Spare memory array 10... Regular memory array, 11... Program element for setting defective address. , 12... Program element for relief decode enable, 13...
Relief decoder, 14...Test decoder six (-r) Completed Figure 2, 3rd item

Claims (1)

[Claims] 1. A unit redundancy decoder that selectively activates a predetermined spare row (or column) includes a group of program elements for setting a defective address, and a group of program elements in which the defective address is set. a program element that indicates that a redundant rescue address signal is generated by the output of the element group only when settings have been made for all of the above element groups; A test address decoding means for generating a redundancy test address signal and a predetermined spare row (
column) a redundant array activation signal generating circuit for generating an activation signal, and a redundant test signal generating circuit for generating the test decode enable signal that is controlled by an external signal and commonly input to all redundant decoders. , comprising a redundant circuit comprising a regular decoding prohibition signal generation circuit that prohibits decoding for selecting a regular array using a regular address only when at least one redundant array activation signal output from the redundant decoder group is activated. A semiconductor memory device characterized by: 2. The redundant test signal generation circuit described above has a supervoltage entry buffer that is activated only when a voltage higher than a predetermined voltage than the power supply voltage is applied to the input terminal, and this output inverts the state of the unbalanced flip-flop. A semiconductor memory device according to claim 1, characterized in that the semiconductor memory device comprises means.