JPH04238199A - Redundancy address selecting circuit - Google Patents

Abstract

PURPOSE:To allow the checking of whether a redundancy memory cell array is good or not before a fuse is blown by providing a redundancy address assigning circuit which directly assigns and selects the addresses of the redundancy memory cell. CONSTITUTION:An address signal X1 and a signal for direct selection of the redundancy address line by the inversion signal thereof are outputted from the redundancy address assigning circuit 3 when a control signal phi is a high level. Transistors(TRs) Q41, Q51 turn off and TRs Q42, 52 turn on and the output terminals N1, N2 of a redundancy address programming circuit 1 attain the low level of an inactive level. Then, the signals outputted from the redundancy address assigning circuit 3 are outputted as the signals RW1, RW2 to set one of the plural redundancy address lines at a selection level from a changeover circuit 6. Whether the redundancy memory cell array is good or not is checked and a defective part is removed before the redundancy address programming circuit is programmed by this constitution.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a redundant address selection circuit, and more particularly to a redundancy address selection circuit that selects an address in a redundant memory cell array to be used as a replacement when a memory cell in a main memory cell array becomes defective.

0002

2. Description of the Related Art In recent years, semiconductor memory devices have been provided with redundant functions in order to avoid a decrease in yield due to higher integration. The redundancy function is operated by signals from the redundancy address selection circuit. A conventional redundant address selection circuit will be explained using a DRAM as an example. To simplify the explanation, only the word line replacement method will be described, but the same applies to the bit line replacement method.

FIG. 2 is a circuit diagram showing an example of a conventional redundant address selection circuit.

The redundant address programming circuits 1 and 2 each have a plurality of redundant address lines for selecting a memory cell in the redundant memory cell array in word units to be used as a replacement when a memory cell in the main memory cell array becomes defective. A plurality of fuses F11 to F14, F21 to F24 and transistors Q11 to Q14, Q21 to Q24 are provided correspondingly and can be cut by a laser or the like, and address signals X0, X1 and their inverted signals are inputted to the address signal X0. , Outputs a signal for

Transistors Q1 and Q2 precharge the output terminals N1 and N2 of the corresponding redundant address programming circuits 1 and 2 to a high level in accordance with the precharge signal A.

When the output control signal B becomes high level, the switching circuit 6a outputs (RW1, RW2) the signals from the redundant address programming circuits 1 and 2 via inverters IV1 and IV2, respectively, and supplies them to each redundant address line. do.

The logic circuit G1 inputs each output signal of the switching circuit 6a, and outputs a signal MWN that stops selecting an address in the main memory cell array when one of the redundant address lines reaches a selection level.

Next, the operation of this redundant address selection circuit will be explained.

Main memory cell array address “01” (
A case where there is a defective memory cell in the address signal (X0=1, X1=0) will be explained. In this case, if the redundant address line corresponding to the redundant address programming circuit 1 is to be selected, fuses F11 and F14 may be cut.

Now, when address signals X0=0 and X1=0 are input, transistors Q11 and Q14 are turned on and transistors Q12 and Q13 are turned off. transistor Q
Since the fuses F11 and F14 connected to the terminals 11 and Q14 are cut, the output terminal N1 of the redundant address programming circuit 1 maintains a high level, and when the output control signal B becomes high level, the switching circuit 6a and the inverter IV1 are switched off. A high level (selection level) signal RW1 is supplied to the corresponding redundant address line through the redundant address line, and a predetermined address of the redundant memory cell is selected. At the same time, a high-level signal MWN is output from the logic circuit G1, and all addresses in the main memory cell array become unselected.

In the redundant address programming circuit 2, since none of the fuses F21 to F24 are cut (not programmed), there is a transistor that is always turned on for all address signals X0 and X1, and the output terminal Set N2 to low level. Therefore signal RW
2 remains at a low non-selection level. Also, in the redundant address programming circuit 1, for address signals other than address signals X0=1 and X1=0,
Since there is a transistor that is always turned on, the signal RW1
is at a low level.

0012

Problems to be Solved by the Invention The conventional redundant address selection circuit described above has fuses F11 to F14, F21 to
Since the configuration is such that one of the redundant address lines is selected by cutting or not cutting F24, it is impossible to restore the fuse once it is cut, so it is possible that a defective memory cell is present in the address of the redundant memory cell array to be used instead. If there was,
This problem cannot be avoided even after replacement, and the semiconductor memory ends up being a defective product, resulting in a lower product yield.

An object of the present invention is to provide a redundant address selection circuit that can confirm the quality of a redundant memory cell array before blowing a fuse, thereby improving product yield.

[0014]

[Means for Solving the Problems] A redundant address selection circuit of the present invention is configured to select memory cells of a redundant memory cell array in a predetermined unit to be used as replacements when a memory cell of a main memory cell array becomes defective. Each of the fuses is provided corresponding to a plurality of redundant address lines, and includes a plurality of fuse elements and transistors to which an address signal is input, and when the address signal specifies an address where a defective memory cell of the main memory cell array exists. a redundant address programming circuit that outputs a signal for setting the corresponding redundant address line to a selected level according to a state of disconnection or non-cutting of an element; a redundant addressing circuit that outputs a signal for setting one of the redundant address lines to a selection level; and when the control signal is at a first level, an output signal of the redundant addressing circuit causes one of the plurality of redundant address lines to be set to a selected level. one of the plurality of redundant address lines is at a selection level, and a switching means for controlling the level of the corresponding redundant address line by the output signal of each of the redundant address programming circuits when at a second level; and one of the plurality of redundant address lines is at the selection level. and a logic circuit that outputs a signal to stop selection of the address of the main memory cell array when the address of the main memory cell array is reached.

[0015]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

The redundant address programming circuits 1 and 2 are constructed similarly to the conventional example shown in FIG. 2, and have similar functions.

When the inverted signal of the control signal Φ is at a low level, the redundant addressing circuit 3 outputs a signal for directly setting one of the plurality of redundant address lines to the selection level using the address signal X1 and its inverted signal. do. Furthermore, when the level is high, these signals are set to a low level, which is an inactive level.

The switching circuits 4 and 5 are provided corresponding to the respective redundant address programming circuits 1 and 2, and when the control signal Φ is at a high level, the output signals of the corresponding redundant address programming circuits 1 and 2 are set to an inactive level. make it low level.

The transistors Q1 and Q2 precharge the output terminals N1 and N2 of the corresponding redundant address programming circuits 1 and 2 via the switching circuits 4 and 5 in accordance with the precharge signal A, as in the conventional example. .

The switching circuit 6 connects the output signals of the respective redundant address programming circuits 1 and 2 and the redundant address designating circuit 3.
Of the corresponding output signals, the signal that is not at the inactive level due to the control signal Φ and its inverted signal is output, respectively. This switching circuit 6 and switching circuit 4,
5 and the redundant addressing circuit, when the control signal Φ is at a high level, the output signal of the redundant addressing circuit sets one of the plurality of redundant address lines to a selection level, and when the control signal Φ is at a low level, each redundant address programming circuit 1 , 2 forms switching means for controlling the level of the corresponding redundant address line.

The logic circuit G1 has the same function as the conventional example.

Next, the operation of this embodiment will be explained.

When the control signal Φ is at a low level, all the outputs of the redundant addressing circuit 3 are at a low inactive level, transistors Q41 and Q51 are turned on, and transistors Q42 and Q52 are turned off, so that the state shown in FIG. The circuit is similar to the conventional example, and the redundant address programming circuits 1 and 2 can select a redundant address line and stop selection of an address in the main memory cell array.

When the control signal Φ is at a high level, a signal for directly selecting a redundant address line is output from the redundant address designating circuit 3 using the address signal X1 and its inverted signal, and transistors Q41 and Q51 are turned off, and the transistor Q42 and Q52 are turned on, and the output terminals N1 and N2 of the redundant address programming circuits 1 and 2 become inactive low level. Therefore, the switching circuit 6 outputs the signal output from the redundant address designating circuit 3 as signals RW1 and RW2 that set one of the plurality of redundant address lines to the selection level. That is, the redundant address designation circuit 3 can directly select a redundant address. This is redundant address programming circuit 1
, 2 before or after programming.

With this configuration, it is possible to check the quality of the redundant memory cell array and remove the defective portion before programming the redundant address programming circuits 1 and 2. This eliminates defective products due to defects in the redundant memory cell array after programming, thereby improving product yield.

Furthermore, after confirming that there are no defective memory cells in the redundant memory cell array by the redundant addressing circuit 3, when the redundant address programming circuits 1 and 2 are programmed to perform a replacement operation using the redundant memory cell array, no defective memory cell is detected. If this occurs, it is found that the cause of the defect is in the redundant address programming circuits 1, 2, etc., other than the redundant memory cell array.

The above-mentioned operation can be performed during wafer testing, but after assembly, the control signal Φ or its inverted signal can be input directly from the outside or generated internally under control from the outside. By activating the redundancy function using the control signal Φ or its inverted signal and writing different data from the main memory cell array into the redundant memory cell array, it is possible to detect the replacement address after assembly, thereby enabling the roll call function. can also be realized at the same time.

[0029]

As explained above, the present invention directly specifies and selects the address of the redundant meoli cell array by setting the control signal to a predetermined level, regardless of whether programming of the redundant address programming circuit is performed or not. By adopting a configuration that includes a redundant address designation circuit, it is possible to check the quality of the redundant memory cell array before programming the redundant address programming circuit, and to remove the defective portion of this redundant memory cell. Eliminate defects due to redundant memory cell array after programming,
This has the effect of improving product yield.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a conventional redundant address selection circuit.

[Explanation of symbols]

1, 2 Redundant address programming circuit 3
Redundant addressing circuits 4 to 6, 6a Switching circuits F11 to F14, F21 to F24 Fuse G1
Logic circuits IV1, IV2 Inverters Q1, Q2, Q11~Q14, Q21~Q24
transistor

Claims (3)

[Claims] 1. Provided in correspondence with a plurality of redundant address lines for selecting, in a predetermined unit, a memory cell of a redundant memory cell array to be used as an alternative when a memory cell of a main memory cell array becomes defective, A plurality of fuse elements and transistors are provided to input an address signal, and when this address signal specifies an address where a defective memory cell of the main memory cell array exists, the fuse element responds according to the cut or non-cut state of each fuse element. a redundant address programming circuit that outputs a signal for setting the redundant address line to a selection level;
a redundant addressing circuit that outputs a signal for setting one of the plurality of redundant address lines to a selection level when the level is at a level of 1 and an inactive level when the control signal is at a second level; When one of the plurality of redundant address lines is set to a selection level by the output signal of the redundant address designating circuit, and when the output signal of each of the redundant address programming circuits is at the second level, the corresponding redundant address line is set to the selected level by the output signal of each of the redundant address programming circuits. It is characterized by comprising a switching means for controlling the level, and a logic circuit that outputs a signal to stop selecting an address of the main memory cell array when one of the plurality of redundant address lines reaches a selection level. Redundant address selection circuit. 2. The redundant address selection circuit according to claim 1, further comprising means for generating the control signal under external control. 3. Switching means is provided corresponding to each redundant address programming circuit, and the control signal is connected to the first one.
a plurality of first switching circuits that set the output signals of the corresponding redundant address programming circuits to an inactive level when the control signal is at a second level; and a redundant address that sets all output signals to an inactive level when the control signal is at a second level. a second switching for outputting the designated circuit, the output signal of each of the redundant address programming circuits, and the corresponding output signal of the redundant addressing circuit, whichever signal is not set to an inactive level by the control signal; 2. The redundant address selection circuit according to claim 1, further comprising a redundant address selection circuit.