JPH0214527A - Semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly proposes a band structure that can reduce the chip size and improve the degree of integration.

FIG. 1 shows the structure of a pad in a conventional integrated circuit.

In the figure, a shaded area 1 indicates an active element area, and 2 indicates a band area. This structure has the disadvantage that the chip size cannot be reduced because an active element area and a pad portion are required within the chip. Furthermore, in the case of internal layer wiring, the wiring area for drawing out signals to the pad portion becomes an obstacle to high integration.

Furthermore, since the insulating film under the pad cannot be thickened, there are disadvantages such as large pad capacitance, slow speed, and increased current consumption.

The present invention aims to solve the various drawbacks of such conventional devices and to obtain a semiconductor device that can further reduce the chip size and increase the density, by introducing new means to its structure and manufacturing method. This is a proposal.

The present invention proposes a semiconductor device comprising the steps of providing an insulating layer on an active region, providing through holes at desired locations in the insulating layer, and forming a pad portion on the active element region. .

The structure of the present invention is shown in FIG. Diagonal line 3 is the active element area,
4 indicates a pad portion. A cross-sectional view of this structure is shown in FIG. The figure shows, as an example, a structure in which a pad portion is provided on a P-type MOS transistor. In the figure, 5 is a semiconductor substrate;
6 is a source and a drain, 7 is a gate oxide film, 8 is an insulating film such as a silicon dioxide film, and 9 is a gate metal such as aluminum, molybdenum, polycrystalline silicon, etc. Reference numeral 10 denotes an interlayer insulating film, and silicon dioxide, phosphosilicate glass, polyimide resin, silicon nitride, or the like may be used, for example. Reference numeral 11 denotes a pad wiring metal, which may be made of, for example, aluminum, molybdenum polycrystalline silicon, chromium, or the like. 12 is a passivation film.

In the above structure, depending on the material and thickness of the interlayer insulating film 10, the reliability of the active element may be impaired by external pressure applied during a functional test of the integrated circuit or bonding with an external device. In order to avoid this, it is also possible to provide a protruding electrode 13 on the metal pad 11 as shown in FIG. 4, thereby creating a structure that can compensate for the external pressure. For example, gold bumps, solder bumps, etc. can be applied.

According to such an invention, the following effects are exhibited.

First, since the pad portion can be formed on the active element region, the chip size can be reduced. Further, since a desired signal line within the integrated circuit can be taken out as a pad portion at an appropriate location, the number of wiring portions can be reduced, the degree of integration can be improved, and circuit testing and connection with the outside can be facilitated.

Furthermore, since the insulating film under the pad can be made thicker, the pad capacitance can be reduced, contributing to higher speed and lower power consumption.

[Brief explanation of the drawing]

FIG. 1 is a structural diagram of a conventional semiconductor device. FIG. 2 is a structural diagram of a semiconductor device according to the present invention. FIGS. 3 and 4 are cross-sectional views showing the structure of a semiconductor device according to the present invention. Applicant Seiko Epson Co., Ltd. Agent Patent attorney Masayoshi Ueyanagi and one other person Figure 2 Figure 3 Figure 54

Claims (1)

[Claims] An interlayer insulating film is further provided on the integrated circuit manufactured on the semiconductor substrate, the wiring metal is multilayered, external connection terminals (butts) are formed with the multilayer wiring metal, and bonding pads are placed on the active element area. 1. A semiconductor device characterized in that a semiconductor device is provided with a portion.