JPH0214531A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a transconductance from being deteriorated by a method wherein an impurity is doped from insulating films, of a second conductivity type, formed on side-wall parts of a conductor layer; low-concentration regions of the second conductivity type are formed and symmetrical regions, of the second conductivity type, to be used as a source region or a drain region are formed on both sides. CONSTITUTION:A gate insulating film 2, a gate electrode 3 and an impurity- containing insulating film 19 are deposited on a substrate 1. Then, impurity- containing side walls 20 are formed only on side-wall parts of the gate electrode 3 by using an etching operation. After that, ions of arsenic as an N-type impurity are implanted into the substrate 1 by making use of the side walls 20 and the gate electrode 3 as a mask. In addition, a heat treatment is executed; high-concentration N<+> regions 5 are formed in regions where ions have been implanted; at the same time, the substrate 1 is doped with an impurity from the side walls 20 on the side of the gate electrode 3 in the N<+> regions 5; low- concentration N<-> regions 4 are formed. In this manner, an LDD structure having the symmetrical low-concentration N<-> regions 4 on both sides of the gate electrode 3 is formed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device, and in particular, an insulated gate (MOS) 711 field effect type having a lightly doped drain (hereinafter referred to as LDD) structure. The present invention relates to a method for manufacturing a semiconductor device.

[Prior Art] FIGS. 3A to 3C are cross-sectional views showing a conventional method for manufacturing this type of semiconductor device in the order of main steps.

First, referring to FIG. 3A, a gate insulating film 2 and a gate electrode 3 are formed on a P-type silicon substrate 1. Using this gate electrode 3 as a mask, a low concentration of N-type impurity is applied to the P-type silicon substrate 1 from the direction indicated by arrow I at a low acceleration voltage.
By performing ion implantation, a low concentration N- region 4, which will become a source or drain region, is formed.

Next, referring to FIG. 3B, a non-doped oxide film 9 is deposited on the entire surface using low pressure CVD (low pressure chemical vapor deposition method, hereinafter referred to as LPGVD).

Finally, as shown in FIG. 3C, this non-doped oxide film 9 is subjected to RIE (Reactive Ion Etchier)
+g) removed by anisotropic etching and gate sidewalls (
The non-doped oxide film 9 is left only on the sidewalls. Thereafter, using the gate electrode 3 and the non-doped sidewall 1o as a mask, high concentration N-type impurities are ion-implanted from the direction indicated by the arrow (■). This results in a high concentration of N
By forming the ten regions 5, an insulated gate field effect semiconductor device having an LDD structure is formed.

[Problem 8 to be solved by the invention] In such a conventional method for forming an LDD structure, in order to prevent channeling, ions are implanted into a semiconductor substrate as shown in FIGS. 3A and 3C. This is done not from a vertical direction, but from a slightly inclined direction. Therefore, a problem has arisen in that the N-type region, which is to become a source or drain region, is formed asymmetrically.

As a result, as shown in FIG. 3A, the electrical resistance of a region 6 in the shadow of the gate electrode 3 and not subjected to ion implantation (hereinafter referred to as a shadow area) increases, leading to a problem in that the transconductance deteriorates. There was a point. Also,
When the source and drain are swapped left and right, there is a problem in that asymmetry occurs in the transistor characteristics.

Therefore, this invention was made to solve the above problems, and it is a semiconductor that can eliminate the asymmetry of a semiconductor region that is to be a source or drain region and prevent deterioration of transconductance. The purpose is to provide a method for manufacturing the device.

[Means for Solving the Problems] According to the method for manufacturing a semiconductor device according to the present invention, first, a semiconductor substrate having a main surface and having a predetermined impurity concentration of a first conductivity type is prepared.

Next, conductive layers are selectively formed at intervals above the main surface of the semiconductor substrate. An insulating film containing second conductivity type impurities is formed on the sidewall portion of the conductor layer. and,
A second conductivity type impurity is ion-implanted into the semiconductor substrate using the conductor layer and the insulating film as a mask. The impurity ions implanted into the semiconductor substrate are diffused to form a highly concentrated second conductivity type semiconductor region within the semiconductor substrate. Along with that,
The impurity contained in the insulating film is doped into the semiconductor substrate, and a low concentration semiconductor region of the second conductivity type is formed under the insulating film and within the semiconductor substrate.

[Operation] In the present invention, impurities are doped from the insulating film containing impurities of the second conductivity type formed on the sidewall portion of the conductor layer, thereby forming a semiconductor of the second conductivity type at a low concentration in the semiconductor substrate. A region is formed.

Therefore, symmetrical second conductivity type semiconductor regions to become source or drain regions can be formed in regions on both sides of the conductor layer.

[Embodiments of the invention] Embodiments of the present invention will be described below with reference to the drawings.

FIGS. 1A to 1D are cross-sectional views showing the first embodiment of the method for manufacturing a semiconductor device according to the present invention in order of steps.

First, referring to the mlA diagram, a gate insulating film 2 and a gate electrode 3, such as an electrode made of a polycrystalline silicon layer, are formed on a P-type silicon substrate 1. In this case, the gate insulating film 2 except under the gate electrode 3 is removed.

Next, referring to FIG. 1B, an impurity-containing insulating film 19 containing N-type impurities is formed on the P-type silicon substrate 1 and the gate electrode 3 by LPGVD or normal pressure CVD.
, for example, phosphorus glass or arsenic-containing glass.

As shown in FIG. 1C, by using RIE anisotropic etching, most of the impurity-containing insulating film 19 on the gate electrode 3 and on the P-type silicon substrate 1 is removed, and the impurity-containing insulating film 19 on the sidewalls of the gate electrode 3 is removed. , are left behind, thereby forming an impurity-containing sidewall 20. Thereafter, using the impurity-containing sidewall 20 and the gate electrode 3 as a mask, arsenic as an N-type impurity is ion-implanted onto the P-type silicon substrate 1 from the direction shown by the arrow ■.

In this case, the ion implantation conditions are approximately 4xlO''/cm2 at an acceleration voltage of 5QkeV.

Furthermore, referring to FIG. 1D, heat treatment is performed to form a high concentration N+ region 5 of about 102'/cm'' in the ion-implanted region.
On the gate electrode 3 side of the + region 5, impurities are doped into the P-type silicon substrate 1 from the impurity-containing sidewall 20 to form an N- region 4 with a low concentration of about 10'8/cm3.

In this way, an LDD structure having symmetrical low concentration N- regions 4 on both sides of the gate electrode 3 can be formed.

In the first embodiment described above, before the impurity-containing insulating film 19 is deposited, the gate insulation @2 is removed from the portions other than under the gate electrode 3. However, in fact, in the manufacturing process of a semiconductor device having an LDD structure, diffusion from the impurity-containing sidewall 20 progresses due to heat treatment performed in other post-processes, and the impurity concentration in the low-concentration N- region 4 decreases. There is a possibility that the depth of the joint portion, etc. may deviate from the optimum value. Therefore, a second embodiment for compensating for such drawbacks will be described below.

FIGS. 2A to 2D are cross-sectional views showing a second embodiment of the method for manufacturing a semiconductor device according to the present invention in order of steps. In addition, in the drawings, parts with the same reference numerals as in FIGS. 1A to 1D indicate the same or equivalent parts.

First, referring to FIG. 2A, there is shown a step before the gate insulating film 2 is removed in areas other than the lower part of the gate electrode 3 in FIG. 1A.

Thereafter, as shown in FIG. 2B, immediately or after the gate insulating film 2 is etched to a predetermined thickness, an impurity-containing insulating film 19 is deposited in the same manner as in the first embodiment.

Further, as shown in FIG. 2C, an impurity-containing sidewall 30 is formed using RIE anisotropic etching as in the first embodiment. At this time, the gate electrode 3
The gate insulating film 2 other than the lower part of the impurity-containing sidewall 30 may be removed at the same time, or may be removed by another etching process. Then the first
Similar to the step shown in FIG. C, N-type impurities are ion-implanted onto the P-type silicon substrate 1.

Finally, as shown in FIG. 2D, heat treatment is performed to form a highly concentrated N+ region 5 in the ion-implanted region.
is formed, and a low concentration N-nR region 4 whose diffusion concentration is controlled according to the thickness of the gate insulating film 2 is formed in the region below the impurity-containing sidewall 30. In this way, a semiconductor device having an LDD structure with controlled diffusion concentration can be manufactured.

Note that in the first or second embodiment described above, the case of an N-channel insulated gate CMO3) field effect semiconductor device was explained, but it is possible to ion-implant P-type impurities into an N-type silicon substrate or an N-type well layer, Alternatively, the present invention is also applicable to the case where a P-channel insulated gate (MOS) field effect semiconductor device is manufactured by forming an insulating film containing P-type impurities on an N-type substrate or an N-type well layer. .

Furthermore, in the above embodiment, an electrode made of a polycrystalline silicon layer was formed as a gate electrode, but a high point metal,
Alternatively, an electrode having a two-layer polycide structure including a polycrystalline silicon layer and a silicide layer may be formed.

[Effects of the Invention] As described above, according to the present invention, low concentration semiconductor regions are formed symmetrically on both sides of the conductor layer by doping from the insulating film containing impurities formed on the sidewalls of the conductor layer. , it is possible to prevent a decrease in transconductance due to the generation of a high resistance region. Moreover, even if the source and drain are exchanged in the semiconductor regions formed symmetrically, a high-performance, highly reliable semiconductor device with symmetrical characteristics can be obtained.

[Brief explanation of the drawing]

FIGS. 1A, 1B, 1C, and 1D are cross-sectional views showing the first implementation of the method for manufacturing a semiconductor device according to the present invention in the order of steps. 2A, 2B, 2C, and 2D show a second method of manufacturing a semiconductor device according to the present invention.
FIG. 3 is a cross-sectional view showing an example in the order of steps. Figure 3A, 3rd
Figures B and 3C are cross-sectional views showing the conventional method of manufacturing a semiconductor device in order of steps. In the figure, 1 is a P-type silicon substrate, 3 is a gate electrode,
4 is an N- region, 5 is an N+ region 19 which is an impurity-containing insulating film, and 20.30 is an impurity-containing sidewall. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Scope of Claims] A step of preparing a semiconductor substrate having a main surface and having a predetermined impurity concentration of a first conductivity type, and selectively spacing a conductor layer above the main surface of the semiconductor substrate. forming an insulating film containing an impurity of a second conductivity type on a side wall of the conductor layer; using the conductor layer and the insulating film as a mask, impurities of a second conductivity type are formed. a step of implanting ions into the semiconductor substrate; diffusing the ion-implanted impurities into the semiconductor substrate;
A high concentration semiconductor region of a second conductivity type is formed in the semiconductor substrate, further doping the semiconductor substrate with an impurity contained in the insulating film, and forming a low concentration semiconductor region under the insulating film and in the semiconductor substrate. forming a second conductivity type semiconductor region.