JPH02145458U - - Google Patents
Info
- Publication number
- JPH02145458U JPH02145458U JP5286189U JP5286189U JPH02145458U JP H02145458 U JPH02145458 U JP H02145458U JP 5286189 U JP5286189 U JP 5286189U JP 5286189 U JP5286189 U JP 5286189U JP H02145458 U JPH02145458 U JP H02145458U
- Authority
- JP
- Japan
- Prior art keywords
- image information
- bus
- image
- slave
- image processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000006870 function Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Multi Processors (AREA)
- Image Processing (AREA)
Description
補正 平１．８．１４ 図面の簡単な説明を次のように補正する。Correction Heisei 1.8.14 The brief description of the drawing has been amended as follows.
【図面の簡単な説明】
本図は本考案の並列分散処理式画像処理装置の
３チヤンネルの実施例の機能ブロツク図で、破線
部ＡはマスターＣＰＵと画像情報制御インターフ
エースと画像情報収納メモリーとスレーブ画像処
理を接続する為のＣＰＵ ＢＵＳ、画像情報ＢＵ
Ｓにて構成されるマスター画像処理を表し、破線
部Ｂ，Ｃはマスター画像処理とＣＰＵ ＢＵＳ、
画像情報ＢＵＳにて接続されるスレーブＣＰＵ及
び画像情報収納メモリーからなるスレーブ画像処
理を表します。[Brief Description of the Drawings] This figure is a functional block diagram of a three-channel embodiment of the parallel distributed processing type image processing device of the present invention. CPU BUS and image information BU for connecting slave image processing
represents the master image processing consisting of S, and the broken line parts B and C represent the master image processing, CPU BUS,
Represents slave image processing consisting of a slave CPU and image information storage memory connected via the image information BUS.
Claims (1)
能とする為、画像情報入力手段から画像情報信号
を取り込む為の画像情報入力制御インターフエー
スと、取り込み画像情報を記憶する画像情報収納
メモリーと、同一画像情報を分散処理を受け持つ
スレーブ画像処理の画像情報収納メモリーに入力
させる為の画像情報ＢＵＳと、スレーブ画像処理
との通信の為のＣＰＵ，ＢＵＳを持ち、スレーブ
画像処理の増設機能を持つたマスター画像処理と
、各々の検索項目の分散処理を受け持ちスレーブ
ＣＰＵと画像情報収納メモリーからなり、ＣＰＵ
，ＢＵＳと画像情報ＢＵＳによりマスター画像処
理と接続されるスレーブ画像処理（複数）からな
る並列分散処理式画像処理装置。 In order to enable parallel and distributed processing of search items in image processing, an image information input control interface for capturing image information signals from image information input means, an image information storage memory for storing captured image information, and an image information storage memory for storing the captured image information, and the same image information. The master image processing unit has an image information BUS for inputting the image information into the image information storage memory of the slave image processing unit that is in charge of distributed processing, and a CPU and BUS for communication with the slave image processing unit, and has an expansion function for the slave image processing unit. It consists of a slave CPU in charge of distributed processing of each search item, and an image information storage memory.
, BUS, and an image information BUS, this is a parallel distributed processing type image processing device consisting of (a plurality of) slave image processing units connected to a master image processing unit via a BUS and an image information BUS.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5286189U JPH02145458U (en) | 1989-05-08 | 1989-05-08 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5286189U JPH02145458U (en) | 1989-05-08 | 1989-05-08 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02145458U true JPH02145458U (en) | 1990-12-10 |
Family
ID=31573534
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5286189U Pending JPH02145458U (en) | 1989-05-08 | 1989-05-08 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02145458U (en) |
-
1989
- 1989-05-08 JP JP5286189U patent/JPH02145458U/ja active Pending
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