JPH02148848A - Manufacturing method of semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a bipolar transistor in which an emitter region and a base region are formed in a self-aligned manner using a polycrystalline silicon film. Regarding the method.

[Conventional technology]

Conventionally, this type of bipolar transistor has been constructed by forming an n-type epitaxial layer 3 on a p-type silicon substrate 1 having an n4-type buried layer 2, as shown in FIG. A collector is formed by insulating and separating with a film 5. Then, a p-type impurity is introduced into the element forming region including the collector to form a first paste layer. Furthermore, polycrystalline silicon 6 containing p-type impurities and silicon oxide film 8 are sequentially formed thereon, and these silicon oxide film 8 and polycrystalline silicon film 6 are selectively removed. Then, impurities are diffused from the polycrystalline silicon film 6 to form a base contact diffusion layer 9.

Thereafter, an insulating film is formed on the etched side surface of the polycrystalline silicon 6, and a polycrystalline silicon film 13 is formed thereon, and an n-type impurity is diffused into the base layer 11 through this polycrystalline silicon film 13. , emitter layer 12
is formed.

[Problem to be solved by the invention]

In the conventional bipolar transistor manufacturing method described above, when etching the polycrystalline silicon film 6, selective etching is required between the polycrystalline silicon film 6 and the epitaxial layer 3, which is single crystal silicon, and the processing and etching conditions must be strictly controlled. This makes manufacturing difficult. Further, in order to reduce the resistance of the polycrystalline silicon film 6, impurities are doped at a high concentration, but these impurities diffuse into the n-type epitaxial layer 3, that is, the base layer 11, due to heat treatment during the manufacturing process. In particular, characteristics tend to deteriorate due to variations in the base concentration directly under the emitter layer 12 or a significant drop in the emitter-base junction breakdown voltage, which poses the problem of requiring very strict manufacturing control.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that facilitates manufacturing and enables improved characteristics such as increased junction breakdown voltage.

[Means to solve the problem]

The method for manufacturing a semiconductor device of the present invention includes the steps of forming a polycrystalline silicon film containing impurities of a second conductivity type on an epitaxial layer of a first conductivity type as a collector, and removing impurities in the polycrystalline silicon film. a step of diffusing into an epitaxial layer to form a second conductivity type diffusion layer; a step of anisotropically etching the polycrystalline silicon film and the epitaxial layer to form a groove; and a step of forming a groove in the epitaxial layer at the bottom of the groove. forming a base layer by introducing impurities of a second conductivity type into the groove; forming a polycrystalline silicon film containing impurities of a first conductivity type in the groove after forming sidewalls on the inner surface of the groove; The method includes a step of diffusing impurities in the polycrystalline silicon film into the base layer to form an emitter layer.

[Effect]

In the above-described manufacturing method, when etching a polycrystalline silicon film to form a groove, there is no need for etching selectivity between the polycrystalline silicon film and the epitaxial layer, simplifying the etching process. . Furthermore, since the base layer is formed on the bottom surface of the trench and is separated from the polycrystalline silicon film by the sidewall, variations in the impurity concentration of the base layer directly below the emitter layer are suppressed, and the base-emitter junction breakdown voltage is improved.

〔Example] Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) to 1(e) are longitudinal sectional views showing a first embodiment of the present invention in the order of manufacturing steps.

First, as shown in FIG. 1(a), an n-type buried layer 2 is formed on a p-type semiconductor substrate 1 made of silicon, and 1.
An n-type epitaxial layer 3 is formed to a thickness of about 0 μm. Then, an insulating region 5 made of a silicon oxide film is formed to define an element formation region. Then, a polycrystalline silicon film 6 is deposited to a thickness of 0.2 to 0.4 .mu.m thereon, and selectively etched so as to remain in predetermined regions including the element forming region.

Further, a p-type impurity of the second conductivity type is introduced into the polycrystalline silicon film 6 on the region where the base is to be formed.

Thereafter, a silicon nitride film 7 is sequentially formed to a thickness of 0.1 to 0.2 μm, and a silicon oxide film 8 is formed to a thickness of 0.3 to 0.5 μm. During the above steps, p-type impurities are diffused from the polycrystalline silicon film 6 to the surface of the n-type epitaxial layer, forming a diffusion layer 9 with a thickness of about 0.3 μm. In some cases, even less is acceptable.

Next, as shown in FIG. 1(b), a silicon oxide film 8. Silicon nitride film7. The polycrystalline silicon film 6 and the epitaxial layer 3, that is, the p-type diffusion layer 9, are sequentially removed to form the groove 10.
form. In this case, there is no need to provide a selectivity in the etching rate between the epitaxial layer 3 and the polycrystalline silicon film 6, and there is no need to set any special conditions.

Next, as shown in FIG. 1C, p-type impurities are introduced into the groove 10 to form the base layer 11 and at the same time the diffusion layer 9. Polycrystalline silicon film 6. and base layer 11 are electrically connected.

Next, as shown in FIG. 1(d), a side wall of, for example, a silicon nitride film 7a is formed on the inner wall of the trench 10. Then, as shown in FIG.

As a widely known method for forming the sidewalls, a silicon nitride film 7a is grown to a thickness of 0.1 to 0.2 .mu.m, and then anisotropic etching is performed to leave the sidewalls intact.

Finally, as shown in FIG. 1(e), a polycrystalline silicon film 13 containing an n-type impurity is formed in the trench 10, and the n-type impurity is diffused from this polycrystalline silicon film 13 into the base layer 11. As a result, the emitter layer 12 is formed within the base layer 11. Thereafter, the bipolar transistor is completed by forming necessary electrode contacts and the like.

Therefore, in this manufacturing method, when etching the polycrystalline silicon film 6, the epitaxial layer 3 is also etched at the same time, so a selective etching technique for polycrystalline silicon and single crystal silicon is not necessary, and this selective etching can be easily performed. becomes possible.

The base layer 11 is formed on the bottom surface of the groove 10 of the epitaxial layer 3, and the sidewall 7 is different from the polycrystalline silicon film 6.
Since they are separated by a, impurities in the polycrystalline silicon film 6 are hardly diffused to the base 111.
This prevents variations in the base concentration directly under the emitter layer 12. At the same time, it improves the emitter-base junction breakdown voltage.

As a result, it is possible to manufacture a bipolar transistor that is easy to manufacture and has stable characteristics.

FIGS. 2(a) to 2(f) are cross-sectional views showing a second embodiment of the present invention in the order of manufacturing steps.

First, as shown in FIG. 2(a), a p-type polycrystalline silicon film 6. Silicon nitride film7. A stacked structure of silicon oxide films 8 is formed.

In this case, a silicon oxide film 4 is formed on the surface of the epitaxial layer 3 to a thickness of 50 to 200 nm.

This silicon oxide film 4 is intended to reduce the area of the diffusion layer of the base and to facilitate the etching of the polycrystalline silicon film 6 in the subsequent process, but it is not absolutely necessary. .

Next, as shown in FIG. 2(b), the silicon oxide film 8. Silicon nitride film7. Polycrystalline silicon film 6. Then, the silicon oxide film 4 is selectively anisotropically etched to form a groove 14.

Next, as shown in FIG. 2C, a second polycrystalline silicon film 6A containing p-type impurities is grown to a thickness of 0.2 to 0.3 μm over the entire surface including the groove 14.

Next, as shown in FIG. 2(d), by forming a silicon nitride film as a second insulating film over the entire surface and anisotropically etching it, sidewalls are formed only on the inner surface of the first trench 14. form 15. Then, the second polycrystalline silicon film 6A and the epitaxial layer 3 are anisotropically etched within the trench 14 to form a narrow trench 10 in which the p-type diffusion layer 9 is removed.

Next, as shown in FIG. 2(e), a p-type impurity is introduced into the bottom surface of this trench 10 to form a base layer 11, and a diffusion layer 9. The second polycrystalline silicon film 6A and the first polycrystalline silicon film 6 are electrically connected.

Finally, as shown in FIG. 2(f), a sidewall 16 of, for example, a silicon nitride film is formed on the inner surface of the trench 10 to insulate the polycrystalline silicon film 6 and the base layer 11, and an A polycrystalline silicon film 13 containing a type impurity is formed, and an n-type impurity is diffused into the base layer 11 from this polycrystalline silicon film 13 to form an emitter 12.

Thereafter, electrode contacts and the like are formed in the same manner as in the first embodiment to complete the bipolar transistor.

In the manufacturing method of this second embodiment as well, the etching process can be simplified, and variations in the concentration of the base layer can be prevented and the breakdown voltage of the base-emitter junction can be improved.

〔Effect of the invention〕

As explained above, in the present invention, the polycrystalline silicon film and the epitaxial layer are simultaneously etched to form the grooves, so when etching the polycrystalline silicon film, etching selectivity is achieved between the etching and the epitaxial layer. This eliminates the need for an etching process. In addition, since the base layer is formed on the bottom of the trench and separated from the polycrystalline silicon film by the sidewall, variations in the impurity concentration of the base layer directly below the emitter layer are suppressed, and the emitter-base junction breakdown voltage is improved. There is an effect that can be done.

[Brief explanation of the drawing]

FIGS. 1(a) to (e) are cross-sectional views showing the first embodiment of the present invention in the order of manufacturing steps, and FIGS. 2(a) to (f) show the second embodiment of the present invention in the order of the manufacturing steps. The sectional view shown in FIG. 3 is a sectional view of a conventional semiconductor device. 1...p-type silicon substrate, 2...n-type buried layer, 3
... N-type epitaxial layer, 4... Silicon oxide film, 5... Insulating region, 6... Polycrystalline silicon film, 6A
...Second polycrystalline silicon film, 7...Silicon nitride film, 7a...Side wall, 8...Silicon oxide film, 9...
・P-type diffusion layer, 10... Groove, 11... Base layer, 1
2... Emitter layer, 13... Polycrystalline silicon film, 1
4... Groove, 15... (side wall) silicon nitride film, 16
...side wall.

Claims (1)

[Claims] 1. Forming a polycrystalline silicon film containing impurities of a second conductivity type on the epitaxial layer of the first conductivity type as a collector, and diffusing the impurities in this polycrystalline silicon film into the epitaxial layer to form a second conductivity type. a step of forming a conductivity type diffusion layer; a step of anisotropically etching the polycrystalline silicon film and the epitaxial layer to form a groove; and doping a second conductivity type impurity into the epitaxial layer at the bottom of the groove. a step of forming a base layer by introducing an impurity into the polycrystalline silicon film; a step of forming a polycrystalline silicon film containing an impurity of a first conductivity type in the trench after forming a sidewall on the inner surface of the trench; a step of diffusing into the base layer to form an emitter layer.