JPH04294543A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable the capacitance between a base and a collector to be reduced and a device to be speeded up by increasing the distance between a conductor for a base electrode lead-out and an epitaxial layer without extending an external base region in a bipolar transistor for leading out the emitter region from a region which is surrounded by the base electrode. CONSTITUTION:An area between an epitaxial layer 3 and a first polycrystal silicon film 7 which is a base electrode is in a multilayer structure of a first nitriding film 5 and a first oxide film 6, and polysilicon is buried in two stages and then is connected to a base layer. At this time, by making thin the first nitriding film 5, a second undercut portion 12 for determining an external base region can be reduced and the distance between the epitaxial layer 3 and the first polycrystal silicon film 7 can be increased by the first oxide film 6, thus enabling the capacitance between the base and collector to be reduced.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having a bipolar transistor.

0002

2. Description of the Related Art FIGS. 3A and 3B show a conventional method of manufacturing an npn type bipolar transistor. As shown in FIG. 3A(a), an n (plus) region 2 is buried in a P-type semiconductor substrate 1.
, a buried p (plus) region (not shown) is formed, and an n-type epitaxial layer 3 is formed with a thickness of about 1 μm. Next, after forming an element isolation oxide film 4 by selective oxidation, a first oxide film 6 with a thickness of about 0.2 μm is formed on the entire surface. Next, a first polycrystalline silicon film 7 is formed on the first oxide film 6 to a thickness of 0.2 μm.
form a degree. Next, boron, which is a P-type impurity, is added to the first
It is introduced into the polycrystalline silicon film 7 using ion implantation and patterned as a base electrode. Next, a first silicon nitride film 5 is formed to a thickness of about 0.1 μm over the entire surface.

Next, as shown in FIG. 3A(b), openings 10 are provided to form each of a base active region and an emitter region, and the first oxide film 6 is exposed. Next, the first oxide film 6 exposed in the opening 10 is etched using the first silicon nitride film 5 as a mask, and the etching is also progressed in the lateral direction to form a first undercut portion 11. Next, a second polycrystalline silicon film 12 is formed so that the first undercut portion 11 is embedded.

Next, as shown in FIG. 3A(c), the second polycrystalline silicon film 12 is etched except for the portion buried in the first undercut portion 11 to form an epitaxial layer that will become a base active region and an emitter region. Expose 3.

Next, as shown in FIG. 3B(d), a BSG film 15, which is a silicon oxide film containing boron, is deposited by vapor phase growth. Next, heat treatment is performed to introduce boron contained in the BSG film 15 into the epitaxial layer 3 to form a p- region 16 which is an active base region. At the same time, the boron introduced into the first polycrystalline silicon film 7 is introduced into the epitaxial layer 3 through the second polycrystalline silicon film 12 embedded in the first undercut portion 11,
A p (plus plus) region 17, which is an external base region, is formed.

Next, as shown in FIG. 3B(e), the BSG film 15 is etched using anisotropic etching to leave only the sidewalls of the openings 10 and expose the epitaxial layer 3 which will become the emitter region. Next, a fourth polycrystalline silicon film 18 doped with arsenic as an N-type impurity is formed over the entire surface, and then patterned to form an emitter electrode so as to be connected to the epitaxial layer 3 whose surface is exposed as an emitter region. . Next, heat treatment is performed to form the third polycrystalline silicon film 1.
Arsenic is introduced into the epitaxial layer 3 from 4 to form an n (plus) region 19 which is an emitter region. At the same time, boron is introduced from the BSG film 15 remaining on the side wall of the opening 10, and the p- region 16 which is the active base region
A p (plus) region 20 which is a link base region for connecting the p (plus plus) region 17 which is an external base region is formed.

[0007]

[Problems to be Solved by the Invention] In this conventional method for manufacturing a semiconductor device, the base-collector capacitance is formed between the first polycrystalline silicon film which is the external base region and the base lead-out electrode, and the n-type region of the epitaxial layer. The capacity is dominant.

In order to reduce the base-collector capacitance and increase the speed of the transistor, the area of the external base region is reduced and the first polycrystalline silicon film serving as the base extraction electrode and the n-type region of the epitaxial layer are distance needs to be increased.

However, when the thickness of the first nitride film is increased in order to increase the distance between the first polycrystalline silicon film and the n-type region of the epitaxial layer, the amount of side etching of the first nitride film is suppressed and the external When the base diffusion region is reduced, the resistance of the polycrystalline silicon film buried to connect the base and the base extraction electrode increases.

Conversely, even if the resistance is reduced by reducing the thickness of the first nitride film, the distance between the first polycrystalline silicon film and the n-type region of the epitaxial layer decreases, making it easy to There was a drawback that the inter-collector capacitance could not be reduced.

An object of the present invention is to provide a method for manufacturing a semiconductor device that solves the above problems.

0012

[Means for Solving the Problems] In order to achieve the above object, in the method for manufacturing a semiconductor device according to the present invention, a first
an insulating film forming step, a second insulating film forming step, a first conductive film forming step, a third insulating film forming step, an opening forming step,
A bipolar transistor having a first undercut formation step, a second conductive film burying step, a second undercut formation step, and a connection region formation step, and an emitter electrode drawn out from within a region surrounded by a base electrode. In the method of manufacturing a semiconductor device, the first insulating film forming step is a step of providing a first insulating film on the semiconductor substrate, and the second insulating film forming step is a step of forming a first insulating film on the first insulating film. The step of forming a second insulating film having etching selectivity with respect to the first insulating film is a step of forming a first conductive film on the second insulating film. The third insulating film forming step is the first
The opening forming step is a step of selectively forming an opening in the third insulating film that reaches the second insulating film, and the first undercut The forming step is a step of etching the second insulating film through the opening to expose the first insulating film, and then proceeding with etching in the lateral direction to form a first undercut portion. is a step of embedding a second conductive film in at least a part of the first undercut portion, and the second undercut forming step is a step of etching the first insulating film through the opening to expose the semiconductor substrate and laterally etching the first insulating film through the opening. This is a step of proceeding with etching to form a second undercut portion, and the connection region forming step is a step of embedding a third conductive film in at least a part of the second undercut portion to form a connection region with the base. It is.

[0013]

[Operation] A first insulating film is provided on the semiconductor substrate, a second insulating film having etching selectivity with respect to the first insulating film is provided on the first insulating film, and a second insulating film is provided on the second insulating film. a first conductive film is provided on the first conductive edge film, a third insulating film is provided on the first conductive edge film, and a third insulating film is provided on the first conductive edge film;
An opening reaching the second insulating film is selectively provided in the insulating film, and the second insulating film is etched through the opening to expose the first insulating film and etching is continued in the lateral direction to form the first underlayer. A cut portion is provided, a second conductive film is buried in at least a portion of the first undercut portion, and the first insulating film is etched through the opening to expose the semiconductor substrate, and etching is continued laterally as well. An undercut portion is provided, and a third conductive film is buried in at least a portion of the second undercut portion to form a connection region with the base.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

(Embodiment 1) FIG. 1 is a sectional view showing Embodiment 1 of the present invention in the order of manufacturing steps.

As shown in FIG. 1A(a), a buried n (plus) region 2 and a buried p (plus) region (not shown) are formed in a p-type semiconductor substrate 1, and an n-type epitaxial layer 3 is formed. 1
It is formed with a film thickness of about μm. Next, element isolation oxide film 4 is formed by selective oxidation. Next, the first nitride film 5 is coated on the entire surface.
Form approximately 1 μm. Before forming the first nitride film 5, the exposed epitaxial layer 3 may be oxidized to form an oxide film of approximately 0.01 μm, which may be used as a buffer between the nitride film and the epitaxial layer (not shown in this example). . Next, a first oxide film 6 is formed on the first nitride film 5 to a thickness of about 0.5 μm, and a first polycrystalline silicon film 7 is formed on the first oxide film 6 to a thickness of about 0.2 μm. Next, boron, which is a P-type impurity, is introduced into the first polycrystalline silicon film 7 by ion implantation and patterned as a base electrode. Next, the second oxide film 8 is coated with a 0.0.
Form approximately 1 μm. Next, a second nitride film 9 of 0.1
It forms about μm.

Next, as shown in FIG. 1A(b), openings 10 are provided to form each of a base active region and an emitter region, and the first oxide film 6 is exposed. Next, using the second silicon nitride film 9 as a mask, the first oxide film 6 exposed in the opening 10 is etched, and etching is continued in the lateral direction to form a first undercut portion 11. Next, a second polycrystalline silicon film 12 is formed so that the first undercut portion 11 is embedded.

As shown in FIG. 1A(c), the second polycrystalline silicon film 12 is etched except for the portion buried in the first undercut portion 11, and the first nitride film 5 is exposed.

As shown in FIG. 1B(d), the second oxide film 8
Using as an etching stopper, the second nitride film 9 and the first nitride film 5 exposed in the opening 10 are etched, and etching is also progressed in the lateral direction to form the second undercut portion 13.
will be established. Next, a third polycrystalline silicon film 14 is formed so that the second undercut portion 13 is embedded. Next, the third polycrystalline silicon film 14 is etched except for the portion buried in the second undercut portion 13 to expose the epitaxial layer 3 that will become the base active region and emitter region.

As shown in FIG. 1B(e), a BSG film 15, which is a silicon oxide film containing boron, is deposited by vapor phase growth. Next, heat treatment is performed to introduce boron contained in the BSG film 15 into the epitaxial layer 3 to form a p- region 16 which is an active base region. At the same time, the boron introduced into the first polycrystalline silicon film 7 is
The epitaxial layer 3 is passed through the second polycrystalline silicon film 12 embedded in the undercut part 11 and the third polycrystalline silicon film 14 embedded in the second undercut part 13.
to form a p (plus plus) region 17 which is an external base region.

As shown in FIG. 1B(f), the BSG film 15 is etched using anisotropic etching to leave only the sidewalls of the openings 10 and expose the epitaxial layer 3 that will become the emitter region. Next, after forming a fourth polycrystalline silicon film 18 over the entire surface, arsenic, which is an N-type impurity, is introduced using an ion implantation method, and patterned so as to be connected to the epitaxial layer 3 whose surface is exposed as an emitter region. to form an emitter electrode. Next, heat treatment is performed to introduce arsenic into the epitaxial layer 3 from the fourth polycrystalline silicon film 18 to form an n (plus) region 19 which is an emitter region. At the same time, boron is introduced from the BSG film 15 remaining on the side wall of the opening 10, and a link is created to connect the p- region 16, which is the active base region, and the p (plus-plus) region 17, which is the external base region. A p (plus) region 20, which is a base region, is formed.

(Embodiment 2) FIG. 2 is a sectional view showing Embodiment 2 of the present invention in the order of manufacturing steps. This embodiment is applied to a bipolar transistor in which selective epitaxial growth is used to form a base.

After performing the steps up to FIG. 1A(c) in the same manner as in Example 1, as shown in FIG. 2(a), the second nitride film 9 and the opening 10 are removed using the second oxide film 8 as an etching stopper.
The exposed first nitride film 5 is etched to expose the epitaxial layer 3, and the etching is also continued in the lateral direction to form a second undercut portion 13. Next, a selective epitaxial layer 21 containing boron as a P-type impurity is grown to a thickness of 0.05 μm on the exposed epitaxial layer 3 using a selective epitaxial growth method. At this time, the third polycrystalline silicon film 14 also grows from the second polycrystalline silicon film 12 and the first polycrystalline silicon film 7 exposed above the opening 10 and the second undercut part 13, and selectively epitaxially It is connected to layer 21.

As shown in FIG. 2(b), the third nitride film 22
After forming about 0.2 μm over the entire surface, it is etched back by anisotropic etching to leave only the side wall of the opening 10. Next, after forming a fourth polycrystalline silicon film 18 on the entire surface,
Introducing arsenic, an N-type impurity, using ion implantation,
An emitter electrode is formed by patterning so as to be connected to the selective epitaxial layer 21 whose surface is exposed as an emitter region. Next, heat treatment is performed to introduce arsenic from the fourth polycrystalline silicon film 18 into the selective epitaxial layer 21 to form an n (plus) region 19 which is an emitter region.

When the base layer is formed using selective epitaxial growth as in this embodiment, the thickness of the base layer is determined by the distance between the n-type epitaxial layer and the polysilicon for leading out the base electrode. Therefore, when an ultra-thin base layer is formed to realize an ultra-high speed bipolar transistor, the thickness of the first nitride film is further reduced, and the capacitance between the collector-base electrode lead polysilicon is reduced by the present invention. Effective for speeding up.

[0026]

As explained above, in the present invention, the insulating film between the n-multiple epitaxial layer and the polysilicon for leading out the base electrode is multilayered, and the polysilicon is buried in two steps to connect it to the base layer. The distance between the collector and the polysilicon for leading out the base electrode can be increased without expanding the external base region, and the capacitance between the base and the collector can be reduced, thereby easily achieving higher speed of the bipolar transistor.

[Brief explanation of drawings]

FIG. 1A is a cross-sectional view showing Example 1 of the present invention in the order of manufacturing steps.

FIG. 1B is a cross-sectional view showing Example 1 of the present invention in the order of manufacturing steps.

FIG. 2 is a cross-sectional view showing Example 2 of the present invention in the order of manufacturing steps.

FIG. 3 is a cross-sectional view showing a conventional example in the order of manufacturing steps.

[Explanation of symbols]

1 P-type semiconductor substrate 2 Embedded n (plus) area 3 Epitaxial layer 4 Element isolation oxide film 5 First nitride film 6 First oxide film 7 First polycrystalline silicon film 8 Second oxide film 9 Second nitride film 10 Opening 11 First undercut part 12 Second polycrystalline silicon film 13 Second undercut part 14 Third polycrystalline silicon film 15 BSG film 16 p-region 17 p (plus plus) area 18 Fourth polycrystalline silicon film 19 n (plus) area 20 p (plus) region 21 Selective epitaxial layer 22 Third nitride film

Claims (1)

[Claims] 1. A first insulating film forming step, a second insulating film forming step, a first conductive film forming step, a third insulating film forming step, an opening forming step, a first undercut forming step,
A method for manufacturing a semiconductor device having a bipolar transistor, which includes a second conductive film embedding step, a second undercut forming step, and a connection region forming step, and an emitter electrode is drawn out from within a region surrounded by a base electrode. The first insulating film forming step is a step of providing a first insulating film on the semiconductor substrate, and the second insulating film forming step is a step of etching the first insulating film on the first insulating film. The step of forming a second insulating film with selectivity is a step of forming a first conductive film on the second insulating film, and the step of forming a third insulating film is a step of forming a first conductive film on a second insulating film. This is a step of providing a third insulating film on the first conductive edge film, and the opening forming step is a step of forming a second insulating film on the third insulating film.
It is a process of selectively providing an opening that reaches the insulating film of
The first undercut forming step is a step in which the second insulating film is etched through the opening to expose the first insulating film, and the etching is also performed in the lateral direction to form a first undercut portion, and the second insulating film is etched through the opening. The embedding step is a step of embedding a second conductive film in at least a part of the first undercut portion, and the second undercut forming step is a step of etching the first insulating film through the opening to expose the semiconductor substrate. This is a step of forming a second undercut portion by proceeding etching in the lateral direction, and in the step of forming a connection region, a third conductive film is buried in at least a part of the second undercut portion to form a connection region with the base. 1. A method of manufacturing a semiconductor device, the step of forming a semiconductor device.