JPH02151925A - Fast bit logic operation device - Google Patents

Abstract

PURPOSE:To speed up bit logic operation processing by allowing a bit logic operation instruction custom LSI to automatically execute bit logic operation without passing a central operation processing part. CONSTITUTION:A bit logic operation frequency counter 14 in the bit logic operation instruction custom LSI 2 counts up the bit logic operation frequency in a bit logic operation execution part 9 and a bit logic operation frequency specifying register 12 specifies the bit logic operation frequency by an instruction outputted from the central operation processing part 1. The contents of the counter 14 are compared with that of the register 12 by a bit logic operation completion detecting part 13 and the completion of bit logic operation is detected. Consequently, a bit logic operation executing part 9 can rapidly execute continuous bit logic operation processing.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high-speed bit logic operation device that performs bit logic operations.

[Prior Art] FIG. 4 is a block diagram (hardware block diagram) showing the configuration of a conventional bit logic operation device.

In the figure, (1) is a central processing unit (CPU) that instructs the custom LSI to execute bit logic operation instructions;
2) is a bit logic operation custom LSI that executes bit logic operations, (4) is a bit logic operation instruction storage memory that stores bit logic operation instructions, and (18) is the bit logic of the bit logic operation custom LSI (2). This is a bit logic operation target data memory that stores data to be operated on. In addition, (101) is an address signal line output from the central processing unit (1), (102) is a control signal line, (
103) is a ready signal line that notifies the central processing unit (1) of cycle completion, and (104) is a data bus.

Further, (5) is a bit logic operation instruction decoding unit that determines the type of bit logic operation instruction from the address signal of the address signal line (101), and (6) is the data bus width ( For example, 8 bit)
A bit position decoding section (7) that selects which bit of data is to be subjected to a bit logic operation generates a timing signal necessary for the bit logic operation using a control signal on a control signal line (102). A bit logic operation timing generation unit (8) is a ready signal generation unit that returns a ready signal to the central processing unit (1) upon completion of a bit logic operation, and (9) is a data memory (18) for bit logic operation.
), the bit logic operation execution section (19) executes a bit logic operation on the data in the bit logic operation execution section (9); The output data read control unit (20) is a data write control unit that writes the operation result of the bit logic operation execution unit (9) to the bit logic operation target data memory (18).

Next, the operation of the conventional bit logic operation device configured as described above will be explained.

First, the central processing unit (1) fetches a bit logic operation instruction from the bit logic operation instruction storage memory (4).

This fetched bit logic operation instruction is a data transfer instruction from a specific address, and this specific address information indicates the type of bit logic operation instruction and the target data of the bit logic operation target data memory (18). Contains information about the address and bit position containing the
When the central processing unit (1) executes this data transfer instruction, the bit logic operation instruction decoder (5) and bit position decoder (6) inside the bit logic operation custom LSI (2) execute the bit logic operation instruction. The information on the type and bit position is sent to the bit logic operation execution section (9), and the bit logic operation is executed according to the timing generated by the bit logic operation timing generation section (7). When the bit logic operation execution unit (9) needs the data in the bit logic operation target data memory (18), it starts the data read control unit (19) and reads data from the bit logic operation target data memory (18). The data is taken into the custom LSI for bit logic operation (2) and bit logic operation processing is executed. Depending on the type of bit logic operation instruction, if it is necessary to write the operation result to the bit logic operation target data memo IJ (18), the data write control unit (2
0) is activated, and the bit logic operation target data memory (1
The calculation result is written in 8).

After completing a series of bit logic operation instructions, the central processing unit (1) reads the bit logic operation target data memory (18), thereby completing the bit logic operation processing.

FIG. 5 shows a schematic flowchart of processing in the case of the conventional example.

First, in step Sll, the central processing unit (1) fetches an instruction from the bit logic operation instruction storage memory (4), and if the result determined in step S12 is not a bit logic operation instruction, in step 813, the CPU Run the cycle. However, if it is determined in step 812 that it is a bit logic operation instruction, the data transfer instruction is executed in step 814, and the custom LSI for bit logic operation (2) determines the type of bit logic operation in step S15. and performs the corresponding bit logic operation. When the execution of the bit logical operation is completed, step S16
The bit logic operation custom LSI (2) outputs a ready signal from the ready signal generation unit (8) to the central processing unit (1), and the central processing unit (1) completes the transfer instruction cycle. .

[Problems to be Solved by the Invention] Since the conventional bit logic operation device is configured as shown below, the intervention of the central processing unit (1) is required for each bit logic operation instruction. , central processing unit (1)
repeats the execution of instruction fetches, resulting in a long processing time.

In view of this, the present invention has been proposed to enable a custom LSI for bit logic operations to automatically execute successive bit logic operation instructions by starting a bit logic operation once in the central processing unit, and to execute bit logic operations at high speed. The objective is to provide a logical operation device.

[Means for Solving the Problems] A high-speed bit logic operation device according to the present invention uses a bit logic operation start address in the bit logic operation instruction storage memory according to an instruction from a central processing unit in a bit logic operation custom LSI. A bit logic operation storage address designation section that specifies the bit logic operation storage, a bit logic operation instruction storage section that stores the bit logic operation instructions from the bit logic operation instruction storage memory, and a bit that specifies the number of bit logic operations by an instruction from the central processing section. A bit logic operation execution unit that executes a bit logic operation using the decoded data from the logic operation count designation register and the above-mentioned bit logic operation instruction storage unit, and a bit logic operation that counts the number of bit logic operations in this bit logic operation execution unit. The bit logic operation completion detection unit compares the contents of the bit logic operation number counter with the contents of the bit logic operation number specification register, detects the completion of the bit logic operation, and notifies the above central processing unit. A RAM for bit logic operations is provided to store the operation results from the execution section.

[Function] The bit logic operation number counter in the custom LSI for bit logic operations in the present invention counts the number of bit logic operations in the bit logic operation execution unit, and the bit logic operation number designation register is configured to receive data from the central processing unit. The bit logic operation count is specified by the instruction, and the contents of the bit logic operation count counter and the bit logic operation count specification register are compared by the bit logic operation completion detection unit to detect the completion of the bit logic operation. , the bit logic operation execution section is capable of executing continuous bit logic operation processing.

[Example] The present invention will be described in detail below.

FIG. 1 is a (hardware) block diagram showing a high-speed bit logic operation device according to an embodiment of the present invention.

In Figure 1, (1) is the central processing unit as in the conventional example, (2) is the custom LSI for bit logic operations, and (3) is the custom LSI for bit logic operations.
is a bit logic operation start address and memory for storing the number of operations, (4) is a bit logic operation instruction storage memory where actual bit logic operation instructions are stored, (5) is a bit logic operation instruction decoding section, and (6) is a bit logic operation instruction decoding section. bit position decoding section,
(7) is a bit logic operation timing generation section, (8) is a ready signal generation section, (9) is a bit logic operation execution section, (1
0) is a bit logic operation start signal generation unit, (11) is a 2-port RAM for bit logic operations that stores data to be subjected to bit logic operations, and (12) is a central processing unit that sets the number of bit logic operations from (1). The bit logic operation number specification register (14) is the bit logic operation timing generation section (
7) is a bit logic operation counter that counts the number of bit logic operations executed based on the generated signal. A bit logic operation completion detection unit detects the completion of the logic operation and notifies the central processing unit (1), and (15) consists of a register that holds the bit logic operation instruction read from the bit logic operation instruction storage memory (4). Bit logic operation instruction storage section, (
16) is a bit logic operation storage address specifying section that sets an address to be given to the memory when reading a bit logic operation instruction, and (17) is a bit logic operation instruction read signal generation section when reading a bit logic operation instruction.

Next, the operation of the high-speed bit logic operation device according to this embodiment will be explained.

FIG. 3 shows a schematic flowchart of processing in a high-speed bit logic operation device according to an embodiment of the present invention, and will be explained using this flowchart.

First, the central processing unit (1) reads a bit logic operation instruction from the bit logic operation instruction storage memory (4) and executes it (step Sl). This bit logic operation instruction basically uses a general-purpose data transfer instruction of the central processing unit (1), and the central processing unit (1) stores the bit logic operation start address and the memory (3) for storing the number of operations. Depending on the contents, the bit logic operation start address and bit logic operation number designation register (12) of the address register of the bit logic operation storage address designation section (16) of the custom LSI for pin I/logic operation (2) are set at the same time. , the bit logic operation start signal generating section (10) instructs the start of bit logic. The bit logic operation custom LSI (2) receives a signal from the bit logic operation start signal generation section (10), causes the bit logic operation timing generation section (7) to generate a timing signal, and uses this timing signal to perform the bit logic operation. The storage address designation section (16) and the bit logic operation instruction read signal generation section (17) are activated, and data of the bit logic operation instruction is transferred from the bit logic operation instruction storage memory (4) to the bit logic operation instruction storage section (15). At the same time, the bit logic operation counter (14) resets the number of bit logic operations (step S2). The data taken into the bit logic operation instruction storage section (15) is decoded by the bit logic operation instruction decoding section (5) and the bit position decoding section (6) to determine the type of bit logic operation instruction and the bit position in the data. It is transmitted to the logical operation execution unit (9). The bit logic operation execution unit (9) reads data from the 2-port RA'M (11) for bit logic operations and executes the bit logic operation (step S3).
). 2 ports R for bit logic operations when reading data
The address of AM (11) is included in the bit logic operation instruction read from the bit logic operation instruction storage memory (4), and is stored in the bit logic operation 2-port RAM ( 11).

When the execution of the bit logic operation by the bit logic operation execution unit (9) is completed, the result of the bit logic operation is stored in the 2-port RAM (11) for bit logic operation, and the bit logic operation number counter (14) is , for example, a bit logic operation execution end signal from the bit logic operation execution unit (9),
Alternatively, the result of the bit logic operation from the bit logic operation execution unit (9) is transferred to the 2-port RAM (11) for bit logic operation.
) is incremented based on the signal etc. at the time of storage. Then, this bit logic operation number counter (14
) is the bit logic operation count specification register (12)
The process of ``-2'' is repeated until the value matches the value of .

That is, based on the bit logic operation execution end signal etc. from the bit logic operation execution unit (9), the data of the next bit logic operation instruction at the same address is sequentially loaded into the bit logic operation instruction storage unit (15). , bit logic operation execution unit (
9) performs bit logic operations. Alternatively, the address of the bit logic operation storage address designation unit (16) is updated based on the bit logic operation execution end signal etc. from the bit logic operation execution unit (9), and the bit logic operation instruction storage memory (4) is sequentially updated. ) is taken into the bit logic operation instruction storage unit (15), and the data from the bit logic operation execution unit (
9) performs bit logic operations.

When the contents of the bit logic operation number counter (14) and the bit logic operation instruction number specification register (12) match, the bit logic operation completion detection unit (13) indicates the completion of a series of bit logic operations to the central processing unit (1). will be notified. By using this completion signal as an interrupt input to the central processing unit (1), it is possible to immediately know the completion of the bit logic operation even if the central processing unit (1) is executing another process.

After bit logic operation is completed, 2-port RA for bit logic operation
The central processing unit (1) reads the contents of M (11) to obtain a bit logic operation result.

FIG. 2 shows an example of data in the bit logic operation instruction storage memory (4), and the 24th to 31st bits are tags indicating that this data is a bit logic operation instruction, and the 16th to 23rd bits are tags indicating that this data is a bit logic operation instruction. The bit is the type of bit logical operation, 1
The 2nd to 15th bits are 2 ports for bit logic operations) -RA
The bit positions in the data in M(11), bits 0 to 11, are 2-port RAM for bit logic operations (11)
This is the address of the data inside.

In addition, in Embodiment 2, the case where the bit logic operation instruction in FIG. Data may be set in the bit logic operation instruction storage section (15) by reading from the memory (4).

[Effects of the Invention] As described above, according to the high-speed bit logic operation device of the present invention, the bit logic operation number counter in the custom LSI for bit logic operations counts the number of bit logic operations in the bit logic operation execution section. In addition, the bit logic operation number specification register specifies the number of bit logic operations based on an instruction from the central processing unit, and the contents of these bit logic operation number counter and bit logic operation number specification register are used to detect the completion of bit logic operations. Since the completion of the bit logic operation is detected by the comparison by the bit logic operation section, the bit logic operation execution section can execute continuous bit logic operation processing.

Therefore, when the central processing unit instructs the bit logic operation instruction custom LSI to start a bit logic operation, the bit logic operation instruction custom LSI automatically executes the bit logic operation without the intervention of the central processing unit. This configuration has the effect of significantly speeding up bit logic operation processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a high-speed bit logic operation device according to an embodiment of the present invention, FIG. FIG. 3 is a schematic flow chart showing bit logic operation processing of a high-speed bit logic operation device according to an embodiment of the present invention, FIG. 4 is a block diagram showing a conventional bit logic operation device, and FIG. 5 is a diagram showing a conventional bit logic operation device. 2 is a schematic flowchart showing bit logical operation processing of FIG. In the figure, 1: Central processing unit 2: Custom LSI for bit logic operations 4: Bit logic operation instruction storage memory 9: Bit logic operation execution unit 11: 2-port RAM for bit logic operations 12: Bit logic operation number specification register 13 2 Bit logic operation completion detection section 14: Bit logic operation number counter 15: Bit logic operation instruction storage section 16: Bit logic operation storage address designation section. In the drawings, the same reference numerals and the same symbols indicate the same or equivalent parts. Agent: Patent attorney Masuo Daikichi and two others Figure 3

Claims (1)

[Scope of Claims] A high-speed bit logic operation device comprising a central processing unit, a bit logic operation instruction storage memory, and a bit logic operation custom LSI, in which instructions from the central processing unit are used in the bit logic operation custom LSI. a bit logic operation storage address specifying section that specifies a bit logic operation start address in the bit logic operation instruction storage memory; and a bit logic operation instruction storage section that stores the bit logic operation instruction from the bit logic operation instruction storage memory. a bit logic operation number specification register that specifies the number of bit logic operations based on an instruction from the central processing unit; and a bit logic operation execution unit that executes the bit logic operation based on decoded data from the bit logic operation instruction storage unit. , a bit logic operation counter for counting the number of bit logic operations of the bit logic operation execution unit; and a comparison of the contents of the bit logic operation counter and the contents of the bit logic operation number specification register to detect completion of the bit logic operation. death,
A high-speed bit logic operation device comprising: a bit logic operation completion detection unit that notifies the central processing unit; and a bit logic operation RAM that stores operation results from the bit logic operation execution unit.