JPH02155248A - Structure of tab - Google Patents
Structure of tabInfo
- Publication number
- JPH02155248A JPH02155248A JP30958488A JP30958488A JPH02155248A JP H02155248 A JPH02155248 A JP H02155248A JP 30958488 A JP30958488 A JP 30958488A JP 30958488 A JP30958488 A JP 30958488A JP H02155248 A JPH02155248 A JP H02155248A
- Authority
- JP
- Japan
- Prior art keywords
- dummy
- tape
- leads
- semiconductor device
- bumps
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 24
- 239000004020 conductor Substances 0.000 claims abstract description 16
- 239000002356 single layer Substances 0.000 claims description 11
- 230000017525 heat dissipation Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 230000002950 deficient Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000000725 suspension Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は導体一層テープを用いたTABの構造に関する
。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to the structure of a TAB using a single layer conductor tape.
従来、この種の長尺テープ状態で電気的選別を行うTA
Bの構造は、第9図に示すように導体パターン26に絶
縁性ベーステープ25により裏打ちを施したものとなっ
ている。27はレジスト、28は半導体装置である。Conventionally, TA performs electrical sorting on this type of long tape.
In the structure B, as shown in FIG. 9, the conductor pattern 26 is lined with an insulating base tape 25. 27 is a resist, and 28 is a semiconductor device.
上述した従来のTABの梢遺は導体に絶縁物を裏打ちし
た構造となっているので、TABテープの構造が複雑と
なり、また使用可能最高温度が料理されるという欠点が
ある。Since the conventional TAB tape mentioned above has a structure in which a conductor is lined with an insulating material, the structure of the TAB tape is complicated and the maximum temperature at which it can be used is increased.
本発明の目的は前記課題を解決したTABの構造を提供
することにある。An object of the present invention is to provide a TAB structure that solves the above problems.
上述した従来のTABの構造に対し、本発明は構造も簡
単でしかも耐熱性が高いという相違点を有する。Compared to the structure of the conventional TAB described above, the present invention is different in that it has a simple structure and high heat resistance.
前記目的を達成するため、本発明に係るTABの構造に
おいては、回路動作部に電気的に導通した主バンプ及び
回路動作部から分離独立したダミーバンプを備えた半導
体装置と、インナーリード及びダミーリードを備えた導
体一層テープとを有し、導体一層テープのインナーリー
ド及びダミーリードを半導体装置の主バンプ及びダミー
バンプにそれぞれ結合するとともに、ダミーバンプに結
合された前記ダミーリードのみを前記導体一層テープか
ら切り離したものである。In order to achieve the above object, the TAB structure according to the present invention includes a semiconductor device including a main bump electrically connected to a circuit operating section and a dummy bump separated and independent from the circuit operating section, and an inner lead and a dummy lead. The inner lead and dummy lead of the single layer conductor tape are respectively coupled to the main bump and the dummy bump of the semiconductor device, and only the dummy lead coupled to the dummy bump is separated from the single layer conductor tape. It is something.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
(実施例1ン
第1図は本発明の実施例1を示す分解斜視図である。半
導体装置1は回路パターン2に電気的に導通した主バン
プ3と、装置の作動に無関係のダミーバンプ4とを有し
ている。この主バンプ3及びダミーバンプ4は金を主体
としたバンプで、底面積は100μmφ直径、25μI
高さのものである。(Embodiment 1) FIG. 1 is an exploded perspective view showing Embodiment 1 of the present invention. A semiconductor device 1 includes main bumps 3 electrically connected to a circuit pattern 2, and dummy bumps 4 unrelated to the operation of the device. The main bumps 3 and dummy bumps 4 are mainly made of gold, and have a bottom area of 100μm diameter and 25μI diameter.
It is of a height.
まなTABテープ5は、予め主バング3及びダミーバン
プ4の位置に合わせてインナーリード6aとダミーリー
ド6bを形成し、1μm厚の金メツキをしたものである
。The TAB tape 5 has inner leads 6a and dummy leads 6b formed in advance in accordance with the positions of the main bang 3 and dummy bumps 4, and is plated with gold to a thickness of 1 μm.
これら半導体装置1とTABテープ5を熱圧着した状態
が第2図である。この状態で各ILBは40g以上の接
続強度を有しているが、各リード6a、 6bが各々導
通しているので、電気的選別は行えない、そこで、第3
図に示すようにダミーバンプ4に結合されたダミーリー
ド6bを除いて、主バンプ3に結合されたインナーリー
ド6aのみを切断し、インナーリード6aの各々のリー
ドをテスターに個々に接続することにより半導体装置1
の電気的選別を可能にするとともに、ダミーリード6b
を吊りリードとして該ダミーリード6bを介して半導体
装置1を導体一層テープ5に支持させて長尺テープ状態
での搬送を可能にする。FIG. 2 shows the semiconductor device 1 and the TAB tape 5 bonded together by thermocompression. In this state, each ILB has a connection strength of 40 g or more, but since each lead 6a and 6b is conductive, electrical selection cannot be performed.
As shown in the figure, excluding the dummy leads 6b connected to the dummy bumps 4, only the inner leads 6a connected to the main bump 3 are cut, and each lead of the inner leads 6a is individually connected to a tester. Device 1
dummy lead 6b.
The semiconductor device 1 is supported by the single-layer conductor tape 5 via the dummy lead 6b by using it as a suspension lead, thereby making it possible to transport the semiconductor device 1 in the form of a long tape.
そのため、電気的選別を行っている最中も半導体装置1
はダミーバンプ4及びダミーリード6bによってTAB
テーテーとつながっているので、第4図に示す自動TA
Bテープ送り機構付きハンドラーで電気的選別を1リー
ル全自動で行うことが可能になる。すなわち、半導体装
置1を備えた長尺テープ状態のTABテープ5を対をな
すリール12.12間に懸は渡し、搬送装置14により
TABテープ5に送りを与えつつ、各半導体装置1にコ
ンタクトヘッド9を接触させてコンピュータ13により
演算処理を行い、不良品を不良打抜きパンチ10でマー
クし電気的選別を行う、11はスペーサである。Therefore, even during electrical sorting, the semiconductor device 1
is TAB by dummy bump 4 and dummy lead 6b.
Since it is connected to the automatic TA shown in Figure 4,
A handler equipped with a B-tape feeding mechanism makes it possible to perform electrical sorting on one reel fully automatically. That is, the TAB tape 5 in the form of a long tape having the semiconductor devices 1 is passed between the pair of reels 12 and 12, and while the TAB tape 5 is fed by the conveying device 14, the contact head is attached to each semiconductor device 1. Reference numeral 11 designates a spacer, which is brought into contact with the spacer 9 and subjected to arithmetic processing by the computer 13, and defective products are marked with a defective punch 10 and electrically sorted.
(実施例2) 第5図、第6図は本発明の実施例2を示す図である。(Example 2) FIG. 5 and FIG. 6 are diagrams showing a second embodiment of the present invention.
半導体装置15は回路パターン16に電気的に導通した
主バンプ17と、装置の作動に無関係のダミーバンプ1
8と、中心部の回路パターンの熱を逃すための伝熱配線
19を有している。また、TABテープ20はインナー
リード21a、ダミーリード21b、放熱部22が一体
に形成しである。The semiconductor device 15 includes a main bump 17 electrically connected to the circuit pattern 16 and a dummy bump 1 unrelated to the operation of the device.
8, and a heat transfer wiring 19 for dissipating heat from the circuit pattern in the center. Further, the TAB tape 20 has an inner lead 21a, a dummy lead 21b, and a heat dissipation part 22 formed integrally.
半導体装置15とTABテープ20を熱圧着ILBし、
電気的選別ができるようにインナーリード21aのみを
切断した状態を第7図に示す。The semiconductor device 15 and the TAB tape 20 are bonded by thermocompression ILB,
FIG. 7 shows a state in which only the inner lead 21a is cut to enable electrical selection.
選別良品になったTABは第8図に示すように放熱部2
2を個々に切断することにより、テープ20の搬送部分
を放熱部22として利用可能となる1本実施例ではダミ
ーバンプ18を半導体装置1の放熱のために利用し、か
つ搬送部分を放熱部22として効率的に利用できるとい
う利点がある。The selected TABs are placed in the heat dissipation section 2 as shown in Figure 8.
By cutting the tape 20 individually, the conveying portion of the tape 20 can be used as the heat dissipating section 22.1 In this embodiment, the dummy bumps 18 are used for heat dissipation of the semiconductor device 1, and the conveying section can be used as the heat dissipating section 22. It has the advantage of being able to be used efficiently.
以上説明したように本発明は半導体装置上に装置の作動
と無関係なダミーバングを設け、それも含めて導体一層
テープにILBL、ダミーバンプとILBされたリード
を除いて、リードを導体一層テープから切断することに
より、長尺テープ形状で電気的選別を行える効果がある
。As explained above, the present invention provides a dummy bump that is unrelated to the operation of the device on a semiconductor device, and cuts the leads from the single-layer conductor tape, excluding the dummy bumps including the dummy bumps and the leads that have been ILBLed to the single-layer conductor tape. This has the effect that electrical sorting can be performed using a long tape shape.
また、ダミーバング及びそれにつながる配線を半導体装
置上の発熱部分付近に配置することにより、半導体装置
の放熱性を上げることができ、しかも、導体一層テープ
上の放熱用パターンをテープ搬送部に掛けて配置するこ
とにより、導体一層テープの効率的利用ができるという
効果がある。In addition, by placing the dummy bang and the wiring connected to it near the heat generating part of the semiconductor device, it is possible to improve the heat dissipation performance of the semiconductor device.Moreover, the heat dissipation pattern on the single-layer conductor tape is placed over the tape transport section. By doing so, there is an effect that the conductor single layer tape can be used efficiently.
第1図〜第3図は本発明の実施例1を示す斜視図、第4
図はTABの選別用設備を示す正面図、第5図〜第8図
は本発明の実施例2を示す正面図、第9図は従来のTA
Bを示す斜視図である。
、15・・・半導体装置 3,17・・・主バング、
18・・・ダミーバンプ
、20・・・導体一層テープ
a、21a・・・インナーリード
b、21b・・・ダミーリード1 to 3 are perspective views showing Embodiment 1 of the present invention;
The figure is a front view showing TAB sorting equipment, Figures 5 to 8 are front views showing Embodiment 2 of the present invention, and Figure 9 is a front view showing a conventional TAB
It is a perspective view showing B. , 15... Semiconductor device 3, 17... Main bang,
18...Dummy bump, 20...Conductor single layer tape a, 21a...Inner lead b, 21b...Dummy lead
Claims (1)
動作部から分離独立したダミーバンプを備えた半導体装
置と、インナーリード及びダミーリードを備えた導体一
層テープとを有し、導体一層テープのインナーリード及
びダミーリードを半導体装置の主バンプ及びダミーバン
プにそれぞれ結合するとともに、ダミーバンプに結合さ
れた前記ダミーリードのみを前記導体一層テープから切
り離したことを特徴とするTABの構造。(1) A semiconductor device having a main bump electrically connected to a circuit operating part and a dummy bump separated and independent from the circuit operating part, and a conductor single-layer tape having an inner lead and a dummy lead. A TAB structure characterized in that an inner lead and a dummy lead are respectively coupled to a main bump and a dummy bump of a semiconductor device, and only the dummy lead coupled to the dummy bump is separated from the conductor single layer tape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63309584A JP2737963B2 (en) | 1988-12-07 | 1988-12-07 | TAB structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63309584A JP2737963B2 (en) | 1988-12-07 | 1988-12-07 | TAB structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02155248A true JPH02155248A (en) | 1990-06-14 |
| JP2737963B2 JP2737963B2 (en) | 1998-04-08 |
Family
ID=17994793
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63309584A Expired - Fee Related JP2737963B2 (en) | 1988-12-07 | 1988-12-07 | TAB structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2737963B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2674681A1 (en) * | 1991-03-28 | 1992-10-02 | Em Microelectronic Marin Sa | ULTRAMINIC ELECTRONIC COMPONENT AND METHOD FOR MANUFACTURING THE SAME |
| US7821115B2 (en) | 2005-12-05 | 2010-10-26 | Nec Electronics Corporation | Tape carrier package including a heat dissipation element |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0245945A (en) * | 1988-08-06 | 1990-02-15 | Seiko Epson Corp | circuit board |
-
1988
- 1988-12-07 JP JP63309584A patent/JP2737963B2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0245945A (en) * | 1988-08-06 | 1990-02-15 | Seiko Epson Corp | circuit board |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2674681A1 (en) * | 1991-03-28 | 1992-10-02 | Em Microelectronic Marin Sa | ULTRAMINIC ELECTRONIC COMPONENT AND METHOD FOR MANUFACTURING THE SAME |
| US7821115B2 (en) | 2005-12-05 | 2010-10-26 | Nec Electronics Corporation | Tape carrier package including a heat dissipation element |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2737963B2 (en) | 1998-04-08 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |