JPH02155308A - Clock distribution circuit - Google Patents

Abstract

PURPOSE:To supply an optional clock to an optional distribution destination in addition to the distribution of a basic clock to respective distribution destination by providing a circuit for clock generation provided with a mask means in addition to a clock distribution means having been in existence in a conventional circuit. CONSTITUTION:When a basic.select clock selection signal 120 from a terminal 12 is logical 0, only a basic select clock distribution circuit 1 is active and a basic clock 190 inputted from a terminal 2 is distributed to clock distribution terminals 7, 8, 9, 10. When the signal 120 is logical 1, a clock select signal 230 supplied to a terminal 5 is fetched by a shift register 18 of a clock select circuit 17. A counter circuit 11 counts the basic clock 190 and when the count is equal to a constant set by a constant setting circuit 13, a comparator circuit 16 outputs logical '1'. An AND circuit 38 ANDs four logic data stored in each stage of the register 18 at this point of time and supplies the result to an OR circuit 5 of the distribution circuit 1, in which the signal is distributed to the terminals 7, 8, 9, 10.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a clock distribution circuit that distributes a basic clock to a plurality of circuit elements of an electronic circuit. This invention relates to a clock distribution circuit that can also distribute clocks.

[Conventional technology]

In conventional clock distribution circuits, when supplying an externally supplied basic clock to an electronic circuit, the waveform of the basic clock is shaped by the number of circuit groups in the electronic circuit that require the clock. The clock was sent to each circuit group.

[Problem to be solved by the invention]

As described above, conventional clock distribution circuits simply shape the waveform of a basic clock supplied from the outside and distribute it to a group of electronic circuits. For this reason, electronic circuits that receive clocks from this clock distribution circuit have only two states: clock running or clock stopped, and only a part of the circuit group cannot operate. There were drawbacks.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a clock distribution circuit that can not only distribute a basic clock to each distribution destination, but also supply a unique clock to each distribution destination if necessary. It is in.

[Means to solve the problem]

In the present invention, the clock distribution circuit is equipped with the following means.

(1) Clock distribution means for distributing the basic clock supplied from the outside to multiple distribution destinations: This means that when the clock selection means, which will be explained later, selects a basic clock, the basic clock is supplied to each distribution destination. It is a circuit that realizes the functions that conventional circuits have.

(11) Counter that counts the basic clock and sets the timing of clock distribution output: This is a means for dividing the basic clock by an arbitrary ratio.

<iii) Mask means for setting for each distribution destination whether or not to output a clock at each timing determined by a counter: This is means for obtaining a clock suitable for each distribution destination.

(1) Clock selection means for selecting either the clock masked by the masking means or the clock distributed by the clock distribution means and outputting it to the respective distribution destinations In this way, the present invention uses the conventional clock distribution method. Since a clock generation circuit including a masking means is provided in addition to the means, it becomes possible to supply any clock to any distribution destination.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows a clock distribution circuit in the case of distributing a basic clock into four or distributing counters with four types of timing types. This clock distribution circuit is composed of a basic/select clock distribution circuit 1, a counter circuit 11, and a r17 select circuit 17. The basic/select clock distribution circuit 1 includes a basic clock input terminal 2, an inverter element 3, an AND element 4,
OR circuit 5, waveform shaping circuit 6 and clock distribution α: 1
(Provided with child 7.8.9 and lO. Counter circuit 11
includes a basic/select clock selection signal input terminal 12, a clock selection signal input terminal 15, a constant setting circuit 13, a counter 14, and a comparison circuit 16.The clock selection circuit 17 includes a shift register 18 and an AND circuit 38. ing.

In this circuit, when a logical value "0" is manually inputted to the basic/select clock selection signal input terminal 12 as the basic/select clock selection signal 120, the circuit operates to divide the basic clock into four parts. In addition, when the logical value "1" is manually set as the basic/select clock selection signal 120, 4
It operates to distribute clocks in different timing formats. That is, the basic/select clock selection signal 120
When the logical value is "0", the output signal of the counter circuit 11 is blocked by the AND element 40, so the AND circuit 38 of the clock select circuit 17 is also blocked, and the output signal is ignored regardless of the basic/select clock distribution circuit 1. Become. Then, only the basic/select clock distribution circuit 1 operates, and the basic clock 190 manually input from the basic clock input terminal 2 passes through the AND element 4 and the basic clock path 30, passes through the OR circuit 5, and is shaped into a waveform by the waveform shaping circuit 6. The clock signal is then distributed to clock distribution terminals 7, 8, 9 and 10, respectively, and supplied to the circuit elements of the electronic circuit.

Next, the basic/select clock selection signal 120 is set to the logical value “
1'', the AND element 4 is off, and the basic clock 190 input from the basic clock input terminal 2 cannot pass through the AND element 4.The clock applied to the clock select signal input terminal 15 of the counter circuit 11 The select signal 230 is taken into the shift register 18 of the clock select circuit 17.
In , the counter 14 counts the basic clock 190 input from the basic clock input terminal 2, and the comparison circuit 16 compares the value with the constant set in the constant setting circuit 13, and when the values become equal, Comparison circuit 16 outputs a logical value "1". This logical value “1” is the AND element 4
0 and reaches an AND circuit 38, where it is ANDed with the four logical data stored in each stage of the shift register 18, and sent to the OR circuit 5 of the basic/select clock distribution circuit 1. These four logical data are sent to the waveform shaping circuit 6, where they are waveform-shaped, and sent out from clock distribution terminals 7, 8, 9 and 10 to external electronic circuits, respectively.

FIG. 2 is a timing chart for explaining the operation of the clock distribution circuit when the clock distribution circuit of this embodiment performs a clock selection operation.

In FIG. 2, 19 is the waveform of the basic clock 190 at the basic clock input terminal 2, 20 is the waveform of the basic/select clock selection signal 120 during clock selection operation, and 22 is the value obtained by counting the basic clock by the counter 14. It is shown in binary numbers.

23 is a clock select signal 230 applied to the clock select signal input terminal 15 during clock select operation.
This is the waveform of Upon receiving the clock select signal 230,
The first stage flip-flop 41 of the shift register 18 is 1
Since the operation is delayed in timing, the clock select signal 24 is adjusted to the timing of this operation.
is shown.

Further, when the tallock select signal 24 has a logical value of "1" or "0", the output signal of the first stage flip-flop 41 similarly has a logical value of "1" or "0". At the same time, the logic value of each flip-flop in the shift register 18 is shifted to the next stage of seven flip-flops. In this embodiment, the constant set in the constant setting circuit 13 is "3", which corresponds to the binary number 11.

Based on the above premise, each of the flip-flops 41, 42, 43 and 44 in the shift register 18 of this embodiment
clock distribution terminals 7.8.9 and 10, respectively.
The timings of the pulse signals sent out are shown at 25, 26, 27 and 28, respectively, in FIG.

These are tarlocks of various timing types, and the four clocks do not necessarily have a logic value of "1" at the same time.

In addition, FIG. 3 shows the basic/select clock selection signal 120.
becomes “0”, and the circuit of this embodiment changes the basic tarok to 4.
This is a timing diagram for explaining the operation of each part in the case of clock distribution, which is similar to the operation of a conventional tarock distribution circuit, and the output signal waveform 2 of the clock distribution terminals 7, 8, 9 and 10.
9 is shown.

〔Effect of the invention〕

As explained above, in the present invention, by controlling the timing of the distributed taroks, it is possible to put a part of the circuit into an operating state or a stopped state, and when evaluating a designed electronic circuit, the evaluation unit can be It has the effect of making it smaller.

[Brief explanation of the drawing]

The drawings are only for explaining one embodiment of the present invention, of which Fig. 1 is a block circuit diagram of a clock distribution circuit, and Fig. 2 is a block circuit diagram of a clock distribution circuit.
The figures are various timing diagrams for explaining the operation of the clock distribution circuit, and FIG. 3 is a timing diagram for explaining the operation of the clock distribution circuit. 1...Basic/select clock distribution circuit, 2...
...Basic clock input terminal, 6...Waveform shaping circuit, 7.8.9.10...Clock distribution terminal, 11
...Counter circuit, 13...Constant setting circuit, 14...Counter, 16...Comparison circuit, 17...Clock selection circuit, 18...
...Shift register, 30...Basic clock bus, 38...AND circuit, 41.42.43.44...Flip-flop, 120...Basic - Select clock selection signal, 190...Basic clock, 230...Tarotsuku selection signal.

Claims (1)

[Scope of Claims] 1. Clock distribution means that distributes a basic clock supplied from the outside to a plurality of distribution destinations; a counter that counts the basic clock and sets the timing of the clock distribution output; masking means for setting whether or not to output a clock at each predetermined timing for each distribution destination; and selecting either the clock masked by the masking means or the clock distributed by the clock distribution means, respectively. 1. A clock distribution circuit comprising: clock selection means for outputting a clock to a distribution destination. 2. The clock distribution circuit according to claim 1, further comprising waveform shaping means for shaping the waveform of the clock output from the clock selection means.