JPH05129936A - Programmable counter - Google Patents

Abstract

PURPOSE:To obtain the programmable counter easily generating a complicated output waveform which has been difficult to be realized by a conventional system. CONSTITUTION:A counter 2 is operated by setting data of an A data register 4 and an overflow output 13 is outputted. A control circuit 6 receiving the output loads setting data of a B data register 5 to the counter 2 and the counter 2 is operated by the data. The operation of the counter 2 (overflow period) is changed by plural data registers to obtain a counter output 14 with a high degree of freedom.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable counter mainly composed of a programmable pulse counter composed of one counter and a plurality of data registers.

[0002]

2. Description of the Related Art A conventional integrated circuit device called a programmable counter will be described below.

FIG. 5 is a block diagram of a conventional integrated circuit device. In FIG. 5, 1 is a frequency dividing circuit for dividing the clock input, 2 is a counter, and 3 is a programmable data register for setting data in the counter 2. 11 is a clock input, 12 is a counter clock, 1
3 is an overflow output, 14 is a counter output,
Reference numeral 15 is a data transmission path.

The operation of the programmable counter configured as described above will be described below.

First, the clock input 11 is frequency-divided by the frequency dividing circuit 1 and input to the counter 2 as the counter clock 12. This counter 2 has a dedicated data register 3, and the data in the data register 3 is
Upon reception of the start time and the overflow output 13, the data is transferred to the counter 2 through the data transmission line 15.

FIG. 6 is a timing diagram of the counter output 14. 6A shows the overflow output 13 and FIG. 6B shows the counter output 14. The overflow cycle T of the counter 2 shown in FIG. 6A is determined by the value of the data register 3, and the counter output 14 has a pulse waveform with a duty ratio of 50% as shown in FIG. ..

[0007]

In the above conventional configuration, the duty ratio of the counter output is always 50%, and two sets of programmable counters are required to change the duty ratio with the overflow cycle.

It is an object of the present invention to provide an integrated circuit device having a very high degree of freedom by realizing the requirement of changing the duty ratio as well as the cycle with a set of programmable counters.

[0009]

In order to achieve this object, a programmable counter of the present invention has a plurality of data registers for one counter and controls the transfer of data from each data register. It is composed of a control circuit.

[0010]

With this configuration, the overflow cycle of one counter has a degree of freedom corresponding to the number of registers. For example, the above-mentioned request to change both the cycle and the duty ratio requires two data. It can be realized by controlling a register.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a programmable counter in the first embodiment of the present invention. In FIG. 1, 1 is a frequency dividing circuit, 2 is a counter, 4 is a data register A,
Reference numeral 5 is a data register B, and 6 is a control circuit.

The operation of the programmable counter configured as described above will be described below.

First, the clock input 11 is frequency-divided by the frequency dividing circuit 1 as in the conventional case, and the counter clock 12
Is input to the counter 2. At the start, the data in the data register 4 is sent to the control circuit 6 via the data transfer path 16 and further to the counter 2 via the data transfer path 18. When the count-up progresses and the counter 2 overflows, the control circuit 6 receives the overflow output 13 and transfers the data of the data register 5 to the counter 2 via the data transmission path 17 and the data transfer path 18 this time. Send in. When the counter 2 overflows again, the next data in the data register 4 is sent to the counter 2. As described above, the data sent to the counter 2 alternates with the data in the data register 4 and the data in the data register 5, so that the counter output 14 is determined by the data in both the data register 4 and the data register 5. However, the pulse waveform has an arbitrary repetition period and duty ratio.

FIG. 2A shows the overflow output 13 of 13 in this embodiment, and FIG. 2B shows the waveform of the counter output 14 of 14 in this embodiment.

In FIG. 2, T1 is an overflow cycle of the counter 2 obtained by the setting data of the data register 4 and T2 is obtained by the setting data of the data register 5, respectively. It goes without saying that the repetition cycle of the counter output 14 is determined by (T1 + T2).

As described above, according to this embodiment, by providing two data registers for one counter, it is possible to arbitrarily change the two factors of the output waveform, that is, the repetition period and the duty ratio. it can.

A second embodiment of the present invention will be described below with reference to FIG. 1 is a frequency divider circuit, 2 is a counter,
Reference numeral 6 denotes a control circuit, which has the same configuration as that of FIG. The difference from the configuration of FIG. 1 is that a data register 7 is further provided in addition to the data register 4 and the data register 5.

The operation of the programmable counter configured as above will be described.

In exactly the same manner as in the first embodiment, the data in the data register 5 is transferred by the control circuit 6 through the data transmission line 17 and the data transmission line 18 to the counter 2.
Then, the control circuit 6 receives the overflow output 13 of the counter 2 and transfers the data in the data register 7 to the data transmission path 19 and the data transmission path 18 this time.
To the counter 2 via.

FIG. 4A is a timing chart of the overflow output 13 in the second embodiment, and FIG. 4B is a waveform chart of the counter output 14.

As described above, by providing the data register C in the second embodiment, it becomes possible to obtain an output waveform with a higher degree of freedom.

The number of data registers forming the programmable counter of the present invention is set to 2 in the first embodiment.
In the second embodiment, the number is three, but it is needless to say that a more complicated output waveform can be realized by further adding the number.

[0024]

As described above, according to the present invention, by providing a plurality of data registers for one counter,
The present invention realizes a programmable counter with a very high degree of freedom, which can easily generate a complicated output waveform with one counter, which is difficult to realize with the conventional method.

[Brief description of drawings]

FIG. 1 is a block diagram of a programmable counter according to a first embodiment of the present invention.

FIG. 2 is a timing chart of overflow output and counter output of the programmable counter according to the first embodiment of the present invention.

FIG. 3 is a block diagram of a programmable counter according to a second embodiment of the present invention.

FIG. 4 is a timing chart of overflow output and counter output in the second embodiment.

FIG. 5 is a block diagram of a conventional programmable counter.

FIG. 6 is a timing diagram of overflow output and counter output of a conventional programmable counter.

[Explanation of symbols]

 1 Frequency Divider 2 Counter 3 Data Register 4 Data Register A 5 Data Register B 6 Control Circuit 7 Data Register C 11 Clock Input 12 Counter Clock 13 Overflow Output 14 Counter Output 15-19 Data Transmission Line

Claims (1)

[Claims] 1. A counter comprising: a counter; a plurality of data registers for loading data into the counter; and a control circuit for controlling data transfer of the respective data registers. , Programmable counter.