JPH0216018B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention makes it possible to inexpensively obtain a semiconductor integrated circuit (hereinafter referred to as a composite I ^{2 L integrated circuit) in which a bipolar circuit and an I 2 L} logic circuit are formed on the same chip. The present invention relates to a method of manufacturing a semiconductor device as described above.

The most common method for manufacturing composite I ² L integrated circuits is to simultaneously diffuse the base of the bipolar transistor and the base of the I ² L transistor, and also to simultaneously diffuse the emitter of the bipolar transistor and the collector of the I ² L transistor. This is the way to do it.

1 to 4 are cross-sectional views showing the state of a semiconductor substrate in each step, in order to explain the manufacturing process of a conventional composite I ² L integrated circuit.

Note that the manufacturing process of the I ² L transistor is shown on the right side of the center of each figure, and the manufacturing process of the bipolar transistor is shown on the left side. The manufacturing process of a conventional composite I ² L integrated circuit will be explained with reference to FIGS. 1 to 4.

First, in FIG. 1, a buried diffusion layer 2 is formed in a semiconductor substrate 1, and an epitaxial layer 3 is formed on it.
is formed. Furthermore, the isolation layer 4 of the bipolar transistor is formed by diffusion of P-type impurities.

Next, the process moves to the step shown in FIG. In the process shown in FIG. 2, N-type impurity diffusion is formed in the epitaxial layer 3 to form the deep collector 5 of the bipolar transistor and the deep collar 6 of the I ² L transistor.

Next, the process moves to the step shown in FIG. 3, and a P-type impurity diffusion layer 7 is formed in the epitaxial layer, thereby forming the base 7 of the bipolar transistor and the injector 9 and base 8 of the I ² L transistor.

Although not shown in FIG. 3,
In the process shown in Figure 3, the diffusion resistance and the lateral
The collector and emitter of a PNP transistor are usually formed at the same time.

Next, proceeding to the step shown in FIG. 4, the emitter 10 of the bipolar transistor and the collector 11 of the I ² L transistor are formed by diffusing N-type impurities inside the base 7 of the bipolar transistor and the base 8 of the I ² L transistor. do.

The above is an ^outline of the conventional method for manufacturing a composite I ² L integrated circuit excluding the contact and electrode wiring processes.
Since this method is based on the process for manufacturing normal bipolar integrated circuits, it has the advantage that composite I ² L integrated circuits can be manufactured relatively easily. Therefore, this process is most commonly used to produce composite I ² L integrated circuits.

However, since a bipolar transistor and an I ² L transistor are formed in the same process, if you try to improve the characteristics of the I ² L transistor, the characteristics of the bipolar transistor will be insufficient; Then,
The characteristics of the I ² L transistor become insufficient.

That is, according to the steps in the conventional manufacturing method, the required characteristics of the two are contradictory. For example, I ² L
In order to sufficiently guarantee fan-out and operating speed of transistors, it is necessary to make the gain as large as possible.

However, increasing the gain of the I ² L transistor is due to the fact that the I ² L transistor operates in the opposite direction.
In order to obtain a predetermined gain as an I ² L transistor, the gain as a normal transistor must be extremely high, sometimes in the hundreds to thousands.

As a result, the withstand voltage between the emitter and collector of a bipolar transistor is significantly lowered, and is usually less than 10V.

Increasing the concentration of the emitter region of the I ² L transistor can improve the carrier injection efficiency and increase the gain of the I ² L transistor without significantly reducing the base width, but it is still possible to increase the gain of the I 2 L transistor without significantly reducing the base width. There is no change in the fact that the withstand voltage tends to decrease.

As a measure to eliminate these drawbacks, base formation, emitter formation, or both may be performed separately for both the I ² L transistor and bipolar transistor, or by burying the I ² L transistor and the bipolar transistor directly under the Some ideas have been proposed, such as changing the impurities in each layer to substances with different diffusion constants, but all of these methods require a significant increase in the number of steps in order to fully demonstrate efficiency, leading to increased costs. ing.

This invention was made to eliminate the above-mentioned conventional drawbacks, and the base and collector of the I ² L transistor of the I ² L logic circuit are formed during the diffusion during isolation formation and deep collector formation, respectively. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can manufacture a composite I ² L integrated circuit that can satisfy the characteristics of both bipolar transistors and I ² L transistors without increasing the number of steps.

Embodiments of the method for manufacturing a semiconductor device of the present invention will be described below with reference to the drawings. FIGS. 5 to 8 are process explanatory diagrams for explaining one embodiment, respectively, and show the state of the wafer cross section in each process. In addition, this figure 5 to 8
In the figure, the left side shows the formation process of a bipolar transistor that forms a bipolar circuit, and the right side shows the formation process of a bipolar transistor that forms a bipolar circuit.
The process of forming an I ² L transistor forming an I ² L logic circuit is also shown.

First, as shown in FIG.
A buried diffusion 16 is applied and an N-type epitaxial layer 13 is grown thereon. Then, in the bipolar transistor section, a P-type diffusion layer 14 is formed in the epitaxial layer 13 in order to perform element isolation.

Note that when forming this P-type diffusion layer 14, the base 15 and injector 17 of the I ² L transistor are formed at the same time. Even if sufficient heat treatment is applied until the P-type diffusion layer 14 reaches the P-type substrate 12, the base 15 and the injector 17 will be removed from the buried diffusion layer 1.
6, each forms a PN junction with the buried diffusion layer 16, and this PN junction is formed directly above the N-type buried diffusion layer 16 from the boundary between the P-type substrate 12 and the epitaxial layer 13. It will be located above the upper diffusion length of layer 16.

Next, the process moves to the step shown in FIG. 6, in which N-type diffusion is performed in order to form the deep collector 18 in the epitaxial layer 13 of the bipolar transistor, and the deep collar 19 and collector 20 of the I ² L transistor, respectively.

Note that the depth of this N-type diffusion is kept at a depth shallower than the final depth in consideration of further progress of diffusion during subsequent heat treatment.

Next, moving to the step shown in FIG. 7, P-type diffusion is performed to form a base 21 in the epitaxial layer 13 of the bipolar transistor.

Furthermore, as shown in FIG. 8, N-type diffusion is performed in the P-type diffusion layer of the base 21 of the bipolar transistor in order to form an emitter 22. The diffusion depth of the N-type diffusion layer of the emitter 22 is set so that the diffusion progresses further during the subsequent heat treatment, and the base width becomes narrower than necessary and the withstand voltage of the bipolar transistor does not decrease. It is necessary to keep it at an appropriate value so that it does not become too small.

Finally, heat treatment is performed to control the gain of the I ² L transistor so that it falls within a predetermined value.

Note that since the gain of a bipolar transistor focuses on the gain of an I ² L transistor, it is difficult to control it with high precision, but normally the gain of a bipolar transistor requires more precise control than the gain of an I ² L transistor. Normally, the circuit is designed so that the I ² L transistor and the bipolar transistor do not have any It is.

As explained above, in the above embodiment, the base and collector of the I ² L transistor are not diffused when forming the base and emitter of the bipolar transistor, respectively, but when forming isolation and deep collector, respectively. Therefore, the junction depths of the base and emitter of the bipolar transistor can be freely controlled without being constrained by the junction depths of the base and collector 20 of the I ² L transistor, respectively.

As a result, increasing the gain of the I ² L transistor does not impair the withstand voltage of the bipolar transistor and does not increase the number of steps, making it possible to manufacture high-performance composite I ² L integrated circuits at low cost. It has the advantage of being able to

As described in detail above, according to the method of manufacturing a semiconductor device of the present invention, the base and collector of the I ² L transistor forming the I ² L logic circuit are separated by diffusion during isolation formation and deep collector formation, respectively. Since the composite I ² L integrated circuit is formed at the same time, it is possible to increase the breakdown voltage of the composite I 2 L integrated circuit using the same simple process as the conventional method without increasing the manufacturing cost.
Along with this, there is an advantage that a composite I ² L circuit including a built-in circuit for driving an external circuit at high voltage can be manufactured at a low cost.

[Brief explanation of drawings]

1 to 4 are process diagrams for explaining a method for manufacturing a semiconductor device, respectively, and FIGS. 5 to 8 are process diagrams for explaining an embodiment of a method for manufacturing a semiconductor device according to the present invention, respectively. It is a diagram. 12... Semiconductor substrate, 13... Epitaxial layer, 14... P-type diffusion layer, 15, 21... Base, 16... Buried diffusion layer, 17... Injector, 18... Deep collector, 19... Deep Color, 20...Collector, 22...Emitsuta.

Claims (1)

[Claims] 1 A step of preparing a first conductivity type semiconductor substrate, a step of forming a buried layer by diffusing a second conductivity type impurity into a bipolar transistor formation region and an I ² L transistor formation region of the substrate, growing an epitaxial layer of a second conductivity type on a substrate including a mixed layer; and selectively diffusing impurities of a first conductivity type to form a layer between the bipolar transistor formation region and the I ² L transistor formation region. A deep collector of the bipolar transistor is formed by simultaneously forming an interelement isolation layer that separates two conductivity type epitaxial layers and the base and injector of the I ² L transistor, and selectively diffusing second conductivity type impurities. and said I ² L
The method includes the steps of simultaneously forming a deep collar and collector of a transistor, and forming a base and an emitter of the bipolar transistor by selectively diffusing impurities of a first conductivity type and an impurity of a second conductivity type, respectively. A method for manufacturing a semiconductor device, characterized in that: