JPH0216112B2 - - Google Patents
Info
- Publication number
- JPH0216112B2 JPH0216112B2 JP4097884A JP4097884A JPH0216112B2 JP H0216112 B2 JPH0216112 B2 JP H0216112B2 JP 4097884 A JP4097884 A JP 4097884A JP 4097884 A JP4097884 A JP 4097884A JP H0216112 B2 JPH0216112 B2 JP H0216112B2
- Authority
- JP
- Japan
- Prior art keywords
- current
- circuit
- mirror circuit
- current mirror
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000006243 chemical reaction Methods 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
- H02M7/02—Conversion of AC power input into DC power output without possibility of reversal
- H02M7/04—Conversion of AC power input into DC power output without possibility of reversal by static converters
- H02M7/12—Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/21—Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/217—Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Rectifiers (AREA)
Description
【発明の詳細な説明】 本発明は、全波整流回路に関する。[Detailed description of the invention] The present invention relates to a full-wave rectifier circuit.
従来の全波整流回路には、交流入力電圧を電圧
で全波整流するようにしたものがある。したがつ
て、従来のものでは、全波整流出力は電圧で得ら
れることになる。ところで、この種の全波整流回
路では、その出力レベルのゲインを簡単に可変す
ることができるようにしたものはなく、通常、全
波整流出力を更に別の増幅器で増幅するなどの構
成が複雑でかつ製造コストも高くつくものとなつ
ている。また、従来のものでは、電圧−電圧変換
のために、全波整流出力のゼロクロス点を得るこ
とが一般には困難である。 Some conventional full-wave rectifier circuits perform full-wave rectification of AC input voltage using voltage. Therefore, in the conventional device, the full-wave rectified output is obtained as a voltage. By the way, in this type of full-wave rectifier circuit, there is no one that allows the gain of the output level to be easily varied, and the configuration is usually complicated, such as amplifying the full-wave rectified output with another amplifier. Moreover, the manufacturing cost has also become high. In addition, in conventional devices, it is generally difficult to obtain the zero-crossing point of the full-wave rectified output due to voltage-to-voltage conversion.
本発明は、上述の事情に鑑みてなされたもので
あつて、簡単な構成で製造コストも安くてすみ、
しかも全波整流出力を簡単に可変できるようにす
るとともに、全波整流出力のゼロクロス点が容易
に得られるようにすることを主たる目的とする。 The present invention has been made in view of the above-mentioned circumstances, and has a simple configuration and low manufacturing cost.
Moreover, the main purpose is to make it possible to easily vary the full-wave rectified output and to easily obtain the zero-crossing point of the full-wave rectified output.
以下、本発明を図面に示す実施例に基づいて詳
細に説明する。図面は、本発明の実施例の回路図
である。この実施例の全波整流回路１は、電圧−
電流変換回路２と、電流出力回路３とを備える。 Hereinafter, the present invention will be described in detail based on embodiments shown in the drawings. The drawing is a circuit diagram of an embodiment of the invention. The full-wave rectifier circuit 1 of this embodiment has a voltage of -
It includes a current conversion circuit 2 and a current output circuit 3.
この電圧−電流変換回路２は、全波整流される
べき交流入力を差動増幅する差動増幅器４を有す
る。この差動増幅器４は、トランジスタＱ２，Ｑ
４を含む。この電圧−電流変換回路２はまた、定
電流源Ｓ１を有するとともに、前記差動増幅器４
の一方の出力端子と他方の出力端子とにそれぞれ
に接続された第１、第２カレントミラー回路５，
６と、第２カレントミラー回路６に接続された第
３カレントミラー回路７とを含む。各カレントミ
ラー回路５，６はそれぞれトランジスタＱ１，Ｑ
６，Ｑ７，Ｑ８を有する。第１カレントミラー回
路５は第３カレントミラー回路７に接続されてい
る。この第３カレントミラー回路７もまた、トラ
ンジスタＱ７，Ｑ８を有する。 This voltage-current conversion circuit 2 has a differential amplifier 4 that differentially amplifies an AC input to be full-wave rectified. This differential amplifier 4 includes transistors Q2, Q
Contains 4. This voltage-current conversion circuit 2 also has a constant current source S1, and the differential amplifier 4
first and second current mirror circuits 5, respectively connected to one output terminal and the other output terminal of the
6 and a third current mirror circuit 7 connected to the second current mirror circuit 6. Each current mirror circuit 5, 6 is a transistor Q1, Q, respectively.
6, Q7, and Q8. The first current mirror circuit 5 is connected to a third current mirror circuit 7. This third current mirror circuit 7 also includes transistors Q7 and Q8.
一方、前記電流出力回路３は、トランジスタＱ
９と、このトランジスタＱ９に接続された第４カ
レントミラー回路８とを備える。この電流出力回
路３はまた、定電流源Ｓ２とダイオードＤ１，Ｄ
２とを有する。 On the other hand, the current output circuit 3 includes a transistor Q
9, and a fourth current mirror circuit 8 connected to this transistor Q9. This current output circuit 3 also includes a constant current source S2 and diodes D1 and D.
2.
第１、第３カレントミラー回路５，７の第１接
続点９に前記トランジスタＱ９と第４カレントミ
ラー回路８との第２接続点１０が共通に接続され
ている。第１カレントミラー回路５から流出され
る第１電流Ｉ１と第３カレントミラー回路７へ流
入される第２電流Ｉ２とが前記両接続点９，１０
で互いに逆方向に流れることにより第３接続点１
１には前記第１、第２の両電流Ｉ１，Ｉ２が同方
向に流れるようになつている。 A second connection point 10 between the transistor Q9 and the fourth current mirror circuit 8 is commonly connected to a first connection point 9 between the first and third current mirror circuits 5 and 7. A first current I1 flowing out from the first current mirror circuit 5 and a second current I2 flowing into the third current mirror circuit 7 are connected to the two connection points 9 and 10.
By flowing in opposite directions to each other, the third connection point 1
1, both the first and second currents I1 and I2 flow in the same direction.
このような構成において、電圧−電流変換回路
２の差動増幅器４の一方の入力端子IN１に図示
の第１交流入力が与えられる。また、その差動増
幅器４の他方の入力端子IN２には第１交流入力
とは反対位相の図示の第２交流入力が与えられ
る。そして、例えば第１交流入力の方が第２交流
入力よりも直流電圧レベルが極端に大きいとき
は、差動増幅器の一方のトランジスタＱ２が導通
し、これに伴ない定電流源Ｓ１で供給される電流
Ｉ０がトランジスタＱ２を介して第１カレントミ
ラー回路５の一方のトランジスタＱ１に流れる。
そうすると、第１カレントミラー回路５の他方の
トランジスタＱ６にトランジスタＱ１に流れた電
流と同じ大きさの電流である第１電流Ｉ１が流れ
ることになる。このとき、第２カレントミラー回
路６には電流が流れていないので、第３カレント
ミラー回路７のトランジスタＱ８は遮断してい
る。したがつて、第１電流Ｉ１は矢符の方向、即
ち電流出力回路３の第２接続点１０の方へ流れ
る。この第１電流Ｉ１により電流出力回路３の第
４カレントミラー回路８におけるトランジスタＱ
１０は導通し、これに伴なつて、同じく第４カレ
ントミラー回路８のトランジスタＱ１１のコレク
タ・エミツタには第１電流Ｉ１が流れる。これに
より、第３接続点１１には第１電流Ｉ１が流れる
ことになる。 In such a configuration, the illustrated first AC input is applied to one input terminal IN1 of the differential amplifier 4 of the voltage-current conversion circuit 2. Further, the other input terminal IN2 of the differential amplifier 4 is supplied with a second AC input shown in the figure having a phase opposite to that of the first AC input. For example, when the DC voltage level of the first AC input is extremely higher than that of the second AC input, one transistor Q2 of the differential amplifier becomes conductive, and as a result, the constant current is supplied by the constant current source S1. A current I0 flows to one transistor Q1 of the first current mirror circuit 5 via the transistor Q2.
Then, the first current I1 having the same magnitude as the current flowing through the transistor Q1 flows through the other transistor Q6 of the first current mirror circuit 5. At this time, since no current is flowing through the second current mirror circuit 6, the transistor Q8 of the third current mirror circuit 7 is cut off. Therefore, the first current I1 flows in the direction of the arrow, that is, toward the second connection point 10 of the current output circuit 3. This first current I1 causes the transistor Q in the fourth current mirror circuit 8 of the current output circuit 3 to
10 becomes conductive, and in conjunction with this, the first current I1 flows through the collector-emitter of the transistor Q11 of the fourth current mirror circuit 8 as well. As a result, the first current I1 flows through the third connection point 11.
次に、第２交流入力の方が第１交流入力よりも
直流電圧レベルが極端に大きいときは、差動増幅
器の他方のトランジスタＱ４が導通し、これに伴
ない定電流源Ｓ１で供給される電流Ｉ０がトラン
ジスタＱ４を介して第２カレントミラー回路６の
一方のトランジスタＱ３に流れる。そうすると、
第２カレントミラー回路６の他方のトランジスタ
Ｑ５にはトランジスタＱ３に流れた電流と同じ大
きさの電流が流れることになる。これにより、第
３カレントミラー回路７のトランジスタＱ８が導
通することにより第２電流Ｉ２が矢符の方向に流
れることになる。このとき、第１カレントミラー
回路５には電流が流れていない。したがつて、電
流出力回路３の第４カレントミラー回路８には電
流が流れないが、トランジスタＱ９はそのベース
にバイアスがかかつているので導通し、これによ
りそのトランジスタＱ９には第１電流Ｉ１と同方
向の第２電流Ｉ２が流れることになる。第１、第
２入力端子IN１，IN２での直流電圧差が極端で
ない場合は、電圧差に応じて電流Ｉ０がトランジ
スタＱ２，Ｑ４に配分され、各カレントミラー回
路５，６，７を介して第１接続点９では電流差Ｉ
１−Ｉ２の絶対値が流れ、それが第３接続点１１
の電流となる。第１、第２入力端子IN１，IN２
での直流電圧差がないときは、電流Ｉ０がトラン
ジスタＱ２，Ｑ４に等分ずつ流れ、電流Ｉ１＝電
流Ｉ２となり、第２接続点１０には電流が流れな
い。これにより、第３接続点１１にも電流が流れ
ない。このようにして、第３接続点１１には差動
増幅器４への交流入力を電圧−電流変換し、これ
を全波整流した図示の電流出力Ｉ１＋Ｉ２が得ら
れる。 Next, when the DC voltage level of the second AC input is extremely higher than that of the first AC input, the other transistor Q4 of the differential amplifier becomes conductive, and as a result, the constant current is supplied by the constant current source S1. Current I0 flows to one transistor Q3 of the second current mirror circuit 6 via the transistor Q4. Then,
A current having the same magnitude as the current flowing through the transistor Q3 flows through the other transistor Q5 of the second current mirror circuit 6. As a result, the transistor Q8 of the third current mirror circuit 7 becomes conductive, so that the second current I2 flows in the direction of the arrow. At this time, no current flows through the first current mirror circuit 5. Therefore, no current flows through the fourth current mirror circuit 8 of the current output circuit 3, but since the base of the transistor Q9 is biased, it becomes conductive, so that the transistor Q9 receives the first current I1 and the current I1. A second current I2 in the same direction will flow. If the DC voltage difference between the first and second input terminals IN1 and IN2 is not extreme, the current I0 is distributed to the transistors Q2 and Q4 according to the voltage difference, and the current I0 is distributed to the transistors Q2 and Q4 via each current mirror circuit 5, 6, and 7. 1 At connection point 9, the current difference I
The absolute value of 1-I2 flows, which is the third connection point 11
The current will be . 1st and 2nd input terminals IN1, IN2
When there is no DC voltage difference between the transistors Q2 and Q4, the current I0 flows equally through the transistors Q2 and Q4, current I1=current I2, and no current flows through the second connection point 10. As a result, no current flows through the third connection point 11 either. In this manner, the AC input to the differential amplifier 4 is subjected to voltage-to-current conversion at the third connection point 11, and the current output I1+I2 shown in the figure is obtained by full-wave rectification.
以上のように、本発明によれば、電圧−電流変
換回路と、電流出力回路とを備え、この電圧−電
流変換回路は、全波整流されるべき交流入力を差
動増幅する差動増幅器と、この差動増幅器の一方
の出力端子と他方の出力端子とにそれぞれの接続
された第１、第２カレントミラー回路と、第２カ
レントミラー回路に接続された第３カレントミラ
ー回路とを含み、前記第１カレントミラー回路は
第３カレントミラー回路に接続されており、前記
電流出力回路は、トランジスタと、このトランジ
スタに接続された第４カレントミラー回路とを備
え、第１、第３カレントミラー回路の第１接続点
に前記トランジスタと第４カレントミラー回路と
の第２接続点が共通に接続されており、第１カレ
ントミラー回路からの第１電流と第３カレントミ
ラー回路への第２電流とが前記両接続点で互いに
逆方向に流れることにより前記トランジスタには
前記第１、第２の両電流が同方向に流れるように
したので、簡単な構成で製造コストも安くてす
み、差動増幅器の共通エミツタに例えば定電流源
を接続し、この定電流源の電流を可変すれば、全
波整流出力を簡単に可変することができるととも
に、電流変換のために全波整流出力のゼロクロス
点が容易に得られるようにすることができる。ま
た、トランジスタの負荷側に抵抗を接続すれば、
この抵抗の両端間に電圧を取り出すことができ
る。さらに、これらをIC化することにより全波
整流出力のオフセツトをゼロにすることもできる
などの利点がある。 As described above, the present invention includes a voltage-current conversion circuit and a current output circuit, and the voltage-current conversion circuit includes a differential amplifier that differentially amplifies an AC input to be full-wave rectified. , including first and second current mirror circuits respectively connected to one output terminal and the other output terminal of the differential amplifier, and a third current mirror circuit connected to the second current mirror circuit, The first current mirror circuit is connected to a third current mirror circuit, and the current output circuit includes a transistor and a fourth current mirror circuit connected to the transistor, and the current output circuit includes a transistor and a fourth current mirror circuit connected to the transistor. A second connection point between the transistor and the fourth current mirror circuit is commonly connected to a first connection point of the transistor, and a first current from the first current mirror circuit and a second current to the third current mirror circuit are connected. flows in opposite directions to each other at the two connection points, so that both the first and second currents flow in the same direction through the transistor, resulting in a simple configuration and low manufacturing cost. For example, by connecting a constant current source to the common emitter of the constant current source and varying the current of this constant current source, the full-wave rectified output can be easily varied, and the zero-crossing point of the full-wave rectified output can be can be easily obtained. Also, if you connect a resistor to the load side of the transistor,
A voltage can be extracted across this resistor. Furthermore, by incorporating these into ICs, there is an advantage that the offset of the full-wave rectified output can be reduced to zero.
図面は、本発明の実施例の回路図である。
１は全波整流回路、２は電圧−電流変換回路、
３は電流出力回路、４は差動増幅器、５，６，
７，８はカレントミラー回路、９，１０，１１は
第１、第２、第３接続点。
The drawing is a circuit diagram of an embodiment of the invention. 1 is a full-wave rectifier circuit, 2 is a voltage-current conversion circuit,
3 is a current output circuit, 4 is a differential amplifier, 5, 6,
7 and 8 are current mirror circuits, and 9, 10, and 11 are first, second, and third connection points.
Claims (1)
え、この電圧−電流変換回路は、全波整流される
べき交流入力を差動増幅する差動増幅器と、この
差動増幅器の一方の出力端子と他方の出力端子と
にそれぞれに接続された第１、第２カレントミラ
ー回路と、第２カレントミラー回路に接続された
第３カレントミラー回路とを含み、前記第１カレ
ントミラー回路は第３カレントミラー回路に接続
されており、前記電流出力回路は、トランジスタ
と、このトランジスタに接続された第４カレント
ミラー回路とを備え、第１、第３カレントミラー
回路の第１接続点に、前記トランジスタと第４カ
レントミラー回路との第２接続点が共通に接続さ
れており、第１カレントミラー回路からの第１電
流と第３カレントミラー回路への第２電流とが前
記両接続点で互いに逆方向に流れることにより前
記トランジスタには前記第１、第２の両電流が同
方向に流れることを特徴とする全波整流回路。1 comprises a voltage-current conversion circuit and a current output circuit, and this voltage-current conversion circuit includes a differential amplifier that differentially amplifies an AC input to be full-wave rectified, and one output terminal of this differential amplifier. and the other output terminal, respectively, and a third current mirror circuit connected to the second current mirror circuit, and the first current mirror circuit is connected to a third current mirror circuit. The current output circuit is connected to a mirror circuit, and the current output circuit includes a transistor and a fourth current mirror circuit connected to the transistor, and the transistor and the fourth current mirror circuit are connected to a first connection point of the first and third current mirror circuits. A second connection point with the fourth current mirror circuit is connected in common, and the first current from the first current mirror circuit and the second current to the third current mirror circuit are directed in opposite directions to each other at the two connection points. A full-wave rectifier circuit characterized in that both the first and second currents flow in the same direction through the transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4097884A JPS60187262A (en) | 1984-03-02 | 1984-03-02 | Full-wave rectifier circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4097884A JPS60187262A (en) | 1984-03-02 | 1984-03-02 | Full-wave rectifier circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60187262A JPS60187262A (en) | 1985-09-24 |
| JPH0216112B2 true JPH0216112B2 (en) | 1990-04-16 |
Family
ID=12595526
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4097884A Granted JPS60187262A (en) | 1984-03-02 | 1984-03-02 | Full-wave rectifier circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60187262A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5448583A (en) * | 1989-08-28 | 1995-09-05 | Fujitsu Limited | Apparatus and method using analog viterbi decoding techniques |
| JPH0729748Y2 (en) * | 1989-10-09 | 1995-07-05 | 新日本無線株式会社 | Rectifier circuit |
| KR100532378B1 (en) * | 1998-04-14 | 2006-02-13 | 삼성전자주식회사 | Full-wave rectifier with offset current prevention circuit |
-
1984
- 1984-03-02 JP JP4097884A patent/JPS60187262A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60187262A (en) | 1985-09-24 |
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