JPH02163973A - Insulated-gate type bipolar transistor - Google Patents

Abstract

PURPOSE:To increase an extraction speed of electrons remaining in an n-type high-resistance layer in an OFF state and, as a result, to enhance an OFF speed by a method wherein a part, of a drain layer, facing a source electrode is made thin. CONSTITUTION:A p-type base layer 4 is formed selectively on the surface part on one side of an n-type high-resistance layer 3; an n-type low-resistance source layer 5 is formed selectively on the surface part of the base layer 4; a gate electrode 8 is formed, via an insulating film 71, on the surface of a channel formation region 6 of the base layer 4 sandwiched between the n-type highresistance layer 3 and the source layer 5. A source electrode 9 is brought into contact with the base layer 4 which is situated on the side opposite to and to be adjacent to the channel formation region 6 of the source layer 5; a p-type low-resistance drain layer 1 is formed on the other side of the n-type high-resistance layer 3 via an n-type low-resistance buffer layer 2; a drain electrode 11 is brought into contact with the p-type drain layer 1. In this assembly, a region, of the p-type drain layer 1, facing the source electrode 9 is made thin; regions 1, 12 in its circumference is made thick.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention utilizes two types of carrier conductivity modulation of electrons and holes in the drain layer of a power MO3FET to reduce the voltage drop in a conductive state. The present invention relates to an insulated gate bipolar transistor (hereinafter abbreviated as MBT).

[Conventional technology]

Although the MBT has a structure similar to a conventional power vertical MOSFET, it contains a bipolar transistor inside and has the advantage of reducing voltage drop in the conductive state by using so-called conductivity modulation. It is something that Its cross-sectional structure is as shown in FIG. 2, in which a high-resistance layer 3 is epitaxially laminated on a p' substrate as a drain layer l with an n-buff 21 layer 2 interposed therebetween. A p-type base layer 4 is formed on the surface thereof, and an n source 115 is further formed on the surface thereof. In order to form an n-channel in the surface layer 6 between the source layer 5 and the high resistance layer 3, a polycrystalline silicon gate electrode 8 is provided with a gate insulating film 71 interposed therebetween. Au is diffused from the surface of the semiconductor element on the side where the gate 1 is provided. and,
The source electrode 9 contacts a part of the source layer 5 and the base layer 4 between them at the opening of the wA green peritoneum 72 that covers the gate electrode 18, but the surface part of the base layer 4 including this contact part
A region 10 is provided. Opposed to this source electrode 9, a drain electrode 11 is in contact with the p-drain layer 1. In such a semiconductor element, when a positive voltage is applied to the source electrode 9 with the gate as the pole 8, an n-channel is formed on the surfaces 1 to 6 of the p-type base layer 4 directly under the gate insulating film 71, and the source Electrons from the layer 5 pass through the channel 6 and are injected into the p' layer l through the zero layer consisting of the high-resistance layer 3 and the low-resistance layer 2, and in response, the p' drain layer 1 to n
゛Hole is injected into n- layer 3 through buff 1 layer 2, n=
Layer 3 causes conductivity modulation and has low resistance. Furthermore, by biasing the gate electrode 1it8i8 to the same potential as the source electrode 9 or to a negative bias, the channel disappears and becomes a blocking state, so that it functions as a so-called switching element.

[Problem to be solved by the invention]

Because this MBT has an MO3 type structure, it has high-speed performance compared to bipolar transistors.
A switching speed of 0 to 200 ns and about 1 μS when off is obtained. By increasing this speed, even more applications are expected. The switching speed is determined by the speed at which the element turns on and the speed at which it turns off, and the off speed in particular is dominated by the speed at which electrons present in the n-layer 3 are extracted. Therefore, the problem is how to extract electrons quickly.

An object of the present invention is to provide an n-channel MBT that can quickly extract electrons in response to the above-mentioned problems.

[Means to solve the problem]

In order to solve the above problems, the present invention selectively forms a p-type base layer on one surface of a high-resistance n-type layer, and further selectively forms an n-type base layer on the surface of the base layer. A gate electrode is provided via an insulating film on the surface of the channel formation region of the base layer, which has a low resistance source layer and is sandwiched between the high resistance n-type layer and the source layer, and is connected to the channel formation region of the source layer. A source electrode is in contact with the surface of the base layer on the opposite side and in contact therewith, and a low-resistance p-type drain layer is provided on the other side of the high-resistance n-type layer via a low-resistance n-type bumper layer, MBT whose drain electrode is in contact with its p-type drain layer
In the p-type drain layer, the region facing the source electrode is thin and the surrounding region is thick.

[Effect]

Since there is a thin region in the p-type drain layer facing the source electrode, the electrons present in the n-type high resistance layer when off are extracted from this thin region without passing through the thick region of the drain layer. A fast off speed is obtained. The thick 9-channel region aids in hole injection through the buffer layer.

〔Example〕

FIG. 1 shows an embodiment of the present invention, and parts common to those in FIG. 2 are given the same reference numerals. In this case, an n-silicon substrate is used, and after forming 2 layers of n-buff on its - side, a layer of 1 to 100-m thick is formed in the same process as the diffusion process used to form pO on the other side. p゛ Drain layer 1 is formed.

Separately, prepare a p′ silicon substrate 12 and use ultrasonic processing to
A hole 13 having a diameter of 0 to 500p is made, and boron is implanted into the entire surface using an ion implantation device to form a p'' drain layer 1.
After bringing the impurity concentration to the same level as above, the surface is lightly etched with hydrofluoric acid. As a result, the holes 13 are inclined. After the surface of the perforated substrate 12 is polished to a smooth surface, it is bonded to the surface of the drain layer l. For adhesion, for example, 1
Heating to 500-800℃ under reduced pressure of 0'□'Pa,
When the electrostatic adhesion method was applied by applying a pulse voltage of 00 to 500 V and 500 m5, the off-speed was improved from the conventional I us to 7 μs when the p silicon base was used, and the variation in characteristics was ± It was about 10%.

FIG. 3 shows another embodiment, in which parts common to FIGS. 1 and 2 are given the same reference numerals. In this case, only the n° buffer layer 2 is formed on one side of the n-silicon substrate, the drain layer 1 is not formed, and the perforated p-silicon substrate 12 is directly bonded to the buffer layer 2. The drain electrode 11 consisting of the Although the formation of layer 1 becomes unnecessary, the p layer and n layer formed at the adhesive interface,
Due to the instability of the bond with the fiber layer, the variation in characteristics is ±
It increased to about 20%.

〔Effect of the invention〕

According to the present invention, by thinning the portion of the drain layer that faces the source electrode, it is possible to increase the extraction speed of electrons remaining in the n-type high-resistance layer during the OFF state, and as a result, the OFF speed can be improved. was completed. Such a structure can be easily obtained by adhering a semiconductor substrate and a perforated semiconductor substrate, and there is no need to use an expensive epitaxial semiconductor substrate, so it is possible to reduce costs.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of an MBT according to an embodiment of the present invention, FIG. 2 is a cross-sectional view of a conventional MBT, and FIG. 3 is a cross-sectional view of an MBT according to another embodiment of the present invention. 1: p layer drain layer, 2: n゛ banff 1 layer, 3: n type high resistance layer, 4: p type base layer, 5: n. Source layer, 6: Channel formation region, 71.72: Insulating film, 8: Gate electrode, 9: Source electrode, 11 Nidrain electrode, 12: P layer silicon substrate, 13: Hole. 0″”)dt4:”Q o M s,. Figure 1

Claims (1)

[Claims] 1) A p-type base layer is selectively provided on the surface of one side of the high-resistance n-type layer, and an n-type low-resistance source layer is selectively provided on the surface of the base layer. A gate electrode is provided on the surface of the channel formation region of the base layer sandwiched between the shape layer and the source layer via an insulating film, and a gate electrode is provided on the surface of the base layer opposite to and adjacent to the channel formation region of the source layer. A source electrode contacts the high-resistance n-type layer, and a low-resistance p-type drain layer is provided on the other side of the high-resistance n-type layer via a low-resistance n-type buffer layer, and the drain electrode contacts the p-type drain layer. An insulated gate bipolar transistor characterized in that the p-type drain layer is thin in the region facing the source electrode and thick in the surrounding region.