JPH02267969A - Horizontal type conductivity modulation type mosfet - Google Patents

Abstract

PURPOSE:To quicken a rise of a current at a time when the current is brought into an ON-state and to contrive the improvement of the currentvoltage characteristics of the title MOSFET without reducing the switching speed of the MOSFET by a method wherein a gate electrode, which forms an inversion region, is provided on the surface of a low-impurity concentration region through a gate oxide film. CONSTITUTION:A 1-mum thick gate electrode 7 is formed of a polycrystalline silicon film over between an N<+> source layer 4 and the exposed surface of an N<-> silicon substrate 1 through a gate oxide film 6. Moreover, a second gate electrode 12 is formed on the surface of the substrate 1 through a gate oxide film 11 and is connected with a gate terminal G'. The film 11 is made thicker than the film 6 because a voltage which is applied to the electrode 12 is higher than a voltage which is applied to the electrode 7 and is formed into a thickness proportionate to the voltage which is applied to the electrode 12. Thereby, the improvement of the current-voltage characteristics of a MOSFET in an ON-state is contrived without reducing the switching speed of the MOSFET.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a lateral conductivity modulated MO3FET in which the base current of a lateral bipolar transistor is supplied by a channel current of a MOSFET, and a control method thereof.

[Conventional technology]

Conductivity modulated MO3FET is an insulated gate bipolar transistor (Insulated Gate Bip
The IGBT is also called an IGBT. An IGBT is known as a voltage-driven bipolar element, and was initially developed as a vertical element, but recently a horizontal IGET has been developed. This is because a vertical IGBT allows current to flow between the front and back surfaces of the semiconductor substrate, whereas a horizontal IGBT is formed using only one side of the semiconductor substrate, making it easier to integrate it into the substrate. This is because it is simple and easy to connect with integrated circuits on the same board.

Figure 2 shows a conventional horizontal N-channel IGBT, with N
- A 20 layer 3 and an N9 source layer 4 in contact with it are provided on the surface of the P well 2 provided on one surface of the Fi, 1 surface, and source electrodes 5 connected to the source terminal S are provided on both layers.
are in contact. A polycrystalline silicon gate electrode 7 is provided between the source layer 4 and the N-substrate region 1 via a gate oxide film 6, and is connected to the gate terminal G. An N' buffer 8721 layer 8 surrounds the Po drain layer 9 at a distance from the P well layer 2, and the P' layer 9 is in contact with a drain electrode 8i10 connected to the drain terminal.

An IGET having such a cross-sectional structure performs switching in the following manner. First, by applying a positive potential to the gate electrode 7, the gate is connected ll! An inversion layer is formed directly below 6, and is also an N channel.

Therefore, electrons pass through the N0 layer 4 from the source side and enter the N- layer 1 via the channel. When these injected electrons enter the P' layer 9 of the N' layer in 8 ways, the P' layer 9 satisfies the neutrality condition.
More holes are injected into the N− layer l via the N′ layer 8. This is conductivity modulation. Due to this conductivity modulation, I GB
T becomes an element with extremely low resistance.

[Problem to be solved by the invention]

However, in the off state, this conductivity-modulated excess carrier only slows down the switching speed. For this reason, devices are usually devised so that carriers are quickly recombined when the recombination center, which is called a lifetime killer, is turned off. However, there was a trade-off relationship in that introducing a large number of lifetime killers promoted recombination and increased resistance in the on state.

Also, if we include the lifetime killer, curve 31 in Figure 3
The I-V characteristic is as shown in Figure 2, and in voltage section A, the source
There are parts where current does not flow even though a voltage is applied between the drains. If you increase the number of lifetime killers mentioned above, section A will expand accordingly, reaching 20
It also reaches V. This is because even if electrons are injected from the source side, they are recombined in the N- layer 1 and therefore do not reach the drain 21 layer 8, so that no holes are injected.

In this way, even if voltage is applied while in the on state, 1
The fact that no current flows is not desirable for a switching element.In order to improve such unfavorable IV characteristics, it is effective to reduce the lifetime killer. If the lifetime killer is reduced, the probability that electrons will reach the drain side will increase, thereby causing injection of holes, and therefore the section A in FIG. 3 will become smaller. However, the switching speed decreases, which is unfavorable in terms of characteristics.

An object of the present invention is to solve the above-mentioned problems and provide a lateral IGBT in which the current rises at a low voltage in the on state without reducing the switching speed.

[Means to solve the problem]

In order to achieve the above object, the present invention selectively attaches a 91st region of a second conductivity type to a surface portion of a semiconductor substrate of a first conductivity type whose lifetime is shortened due to a low impurity concentration. A second region of the second conductivity type is located at a predetermined interval, and a third region of the second conductivity type and a fourth region of the first conductivity type, both of which have a high impurity concentration, are selectively formed on the surface of the second region. The third region and the fourth region are short-circuited by a source electrode, a gate electrode is provided on the surface of the first region between the fourth region and the substrate region via an oxide film, and a surface portion of the second region is In a lateral IGBT in which a fifth region of the second conductivity type with a high impurity concentration is selectively formed in contact with the drain electrode, an oxide film is formed on the surface of the semiconductor substrate exposed between the first region and the second region. It is assumed that a second gate electrode is provided through the gate electrode.

[Effect]

When a voltage is applied to the gate electrode provided through the oxide film on the surface of the substrate exposed between the first region and the second region, an inversion region is formed in the substrate surface layer between the first region and the second region. Therefore, one carrier injected from the source side quickly reaches the drain side through this inversion region without recombining, causing injection of the other carrier, and a current flows between the source and drain. As a result, the area in which no current flows even when a voltage is applied between the source and drain is narrowed.

〔Example〕

FIG. 1 shows a horizontal IGBT of the present invention, and parts common to those in FIG. 2 are given the same reference numerals. In this case, the group +
The layer i structure formed in the iil is the same as the conventional example shown in FIG. In other words, by selective diffusion from the surface to the N-silicon substrate 1 with a resistivity of 50 to 100 Ω, a width of 40 to 5
P with a surface impurity concentration of 5×101th/cd at 0 Ifm
Well (first region) 2 and surface impurity concentration approximately 10” /
cj N° buffer layer (second region) 8 is 50 to 100
They are formed with an interval d of n.

The dimension d varies depending on the withstand voltage of the element, for example, when the withstand voltage is 12
00V, M plate specific resistance is 100Ω in countries, it is set to 100-, and P well 2 is further selectively diffused from the surface to a depth of 4 to 5-1 with a surface impurity concentration IQ + 9/- or more P' contact layer (No. A third region) 3 and a fourth region) 4 of the N" source layer with a depth of 1-1 and a surface impurity source density of about 10"/- are provided.On the other hand, the N" buffer layer 8 is also provided with selective impurities from the surface. Width 20-3 Q, w, depth 4-5 with diffusion
n, P゛ drain layer with surface impurity concentration of about 10”/-
(Fifth area) 9 is provided. An impurity concentration of 10"/cd is formed between the N0 source layer 4 and the N-substrate 1 exposed on the surface through a gate oxide film 6 with a thickness of 1000 nm.
The gate electrode 7 is made of polycrystalline silicon and has a thickness of 1n. Furthermore, the exposed N-substrate 1 according to the present invention
A second gate electrode 12 is formed on the surface of the gate electrode 12 via a gate oxide film 11, and is connected to the gate terminal G'. Gate oxide film 11 is made thicker than gate oxide film 6 because the voltage applied to second gate electrode 12 is higher than the voltage applied to gate electrode 7 . Therefore, the second gate 1tfi
The thickness is determined according to the voltage applied to 12.

That is, after forming an oxide film with a thickness of 1000 nm on the surface of the substrate 1, the region where the gate electrode 8i7 is provided is covered with a nitride film, and further oxidation is performed. gate t
8i7 and 12 were formed by simultaneously depositing polycrystalline silicon on the oxide films having different thicknesses and then separating them. Although a lifetime killer such as gold is introduced into the substrate 1 from the back surface, the lifetime may be shortened by electron beam irradiation.

When trying to turn on such a lateral IGBT with a voltage applied between the drain terminal and the source terminal S, not only a voltage is applied to the gate terminal G, but also a voltage is applied to the gate terminal G'. When this is applied, a low-resistance inversion region is formed in the surface layer of the substrate 1 between the P well 2 and the N° buffer layer 8, creating a path for electrons injected from the source side, and easily transferring electrons to the drain side. can be reached.

As a result, holes are easily injected from the P drain layer 9, and the I-V characteristic is changed by the line 3 in FIG.
As shown by 2, the section where current does not flow is much smaller than in the conventional A. However, only the part corresponding to the built-in potential of the PN junction on the drain side is necessary for the current to rise, but its value is less than 1.2V and can be ignored when compared to the conventional 20V.

In the above embodiment, an N-channel lateral IGBT was described, but a P-channel lateral IGBT having the opposite conductivity type of each layer is used.
The same procedure can be applied to T as well.

〔Effect of the invention〕

Is the present invention a low impurity concentration with a shortened lifetime due to the introduction of a lifetime killer? In order to prevent the carriers injected in the region (2) from recombining and not reaching the drain side, an inversion region is formed on the surface of the low impurity concentration region at the gate 'r! By providing one pole through the gate oxide film, the rise of the current when turning on is extremely fast, and the i
A lateral IC; BT with improved s-voltage characteristics could be obtained.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a lateral rGBT according to an embodiment of the present invention, FIG. 2 is a cross-sectional view of a conventional lateral IGBT, and FIG. 3 is a current-voltage characteristic of a lateral rGBT according to a conventional and an embodiment of the present invention. It is a line diagram. 1: N-silicon substrate, 2: P well (first region)
31p" contact layer (third region) 4: N" source layer (fourth region) 5: source electrode, 6, 11: gate oxide film, 7: gate electrode, 8: N0 buffer layer (second region) 9: 11747th layer (fifth 61st area) 10 Ni dorain electrode, 12: No. 1 electrode. ? )-1 bite

Claims (1)

[Claims] 1) A first region of a second conductivity type and a second region of a first conductivity type are selectively formed at a predetermined interval on the surface of a semiconductor substrate of a first conductivity type whose lifetime is shortened due to a low impurity concentration. A third region of the second conductivity type and a fourth region of the first conductivity type, both of which have a high impurity concentration, are selectively formed on the surface of the first region. A gate electrode is provided on the surface of the first region between the fourth region and the substrate region via an oxide film, and the second region is short-circuited by the electrode, and the second region has a highly impurity-concentrated second conductor in contact with the drain electrode. The fifth region of the shape is selectively formed, and the second gate electrode is provided on the surface of the semiconductor substrate exposed between the first region and the second region with an oxide film interposed therebetween. Horizontal conductivity modulation type MOSFET.