JPH0216575B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of the Invention) The present invention relates to a semiconductor device, and particularly to a semiconductor device using a high melting point metal as an electrode or the like, and a method for manufacturing the same.

(Prior art and its drawbacks) Conventionally, in semiconductor devices, aluminum (hereinafter referred to as "Al") has been used as a material for electrodes, wiring, etc.
Low melting point metals such as molybdenum (hereinafter referred to as "Mo"), tungsten (hereinafter referred to as "W"), tantalum (hereinafter referred to as "Ta"), titanium (hereinafter referred to as "Ti")
High melting point metals such as (hereinafter referred to as "poly Si") or semiconductor materials such as polycrystalline silicon (hereinafter referred to as "poly Si") were used. Each of these materials had advantages and disadvantages. In other words, although Al has the advantage of low resistivity, its melting point is as low as 660°C, so there are various restrictions when introducing it into the manufacturing process of semiconductor devices, which usually requires a heat treatment process of about 1000°C. was. On the other hand, polySi has the advantage of being able to withstand heat treatment at about 1000° C. and having a high affinity with silicon used as a substrate, allowing a greater degree of freedom in the manufacturing process of semiconductor devices. Furthermore, by simply heat-treating poly Si in an oxidizing atmosphere, a silicon oxide film (hereinafter referred to as "SiO ₂ ") with good insulation can be easily formed on the surface of poly Si, and both poly Si and SiO ₂
The element surface can be easily cleaned because it can withstand acid cleaning (hereinafter simply referred to as "acid cleaning") with an appropriate mixture of solutions such as H ₂ SO ₄ , HCl, HNO ₃ , H ₂ O ₂ , etc. Therefore, when poly Si is used for electrodes, wiring, etc., there is an advantage that the manufacturing yield of semiconductor devices is high. However, the specific resistance of poly Si is two to three orders of magnitude higher than that of metals, so semiconductor devices that use poly Si for electrodes, wiring, etc., increase propagation delay due to wiring resistance, achieving higher integration and higher speed. It was difficult to do so.

On the other hand, high-melting point metals such as Mo have a high melting point of about 2600℃ and can withstand heat treatment of about 1000℃, so using Mo for electrodes, wiring, etc. can increase the degree of freedom in the manufacturing process of semiconductor devices. Since high melting point metals have low specific resistance, they are also suitable for increasing the speed of semiconductor devices. For this reason, semiconductor devices including high-melting point metals have been in the spotlight. However, in the case of high-melting-point metals compared to poly-Si, a semiconductor device with a structure that has a stable and high-quality insulating layer like a silicon thermal oxide film on its surface, and a method for easily manufacturing it, have not been realized. As a result, semiconductor devices using high-melting point metals for electrodes, wiring, etc. could not become mainstream in semiconductor technology until now. Structures in which an insulating layer such as a silicon oxide film is provided on a high-melting point metal layer have existed in the past. However, since this silicon oxide film is formed by a chemical vapor deposition (hereinafter referred to as "CVD") method (hereinafter a silicon oxide film formed by the CVD method is referred to as "CVDSiO ₂ "), the film quality is poor. The problem was that, for example, the dielectric strength was lower than that of thermally oxidized silicon films. Furthermore, the CVD method deposits CVDSiO ₂ on the entire surface, and cannot selectively form a silicon oxide film only on the high melting point metal surface. Furthermore this CVDSiO ₂
It is difficult to form CVDSiO 2 with a uniform thickness over stepped areas, and CVDSiO ₂ often forms an overhang at stepped areas. For this reason this CVDSiO ₂
When trying to realize a semiconductor with a three-layer structure consisting of a refractory metal layer with steps, CVDSiO ₂ , and other conductive layers by using it as an interlayer insulating film, there was a drawback that there were many short circuits or disconnections. In addition, to form CVDSiO ₂ on the surface of a high-melting point metal using the CVD method,
In order to prevent oxidation of the high melting point metal, the temperature inside the CVD device must be lowered before using the sample containing the high melting point metal.
Install it in the CVD equipment, create an inert atmosphere inside the equipment, raise the temperature, and then supply the reaction gas into the equipment.
CVDSiO ₂ had to be formed. This has resulted in the drawback that the operation is complicated and takes a long time. In addition, in the conventional method, the withstand voltage of CVDSiO ₂ ,
To eliminate problems such as the presence of pinholes
CVDSiO ₂ had to be thick, for example, 5000 Å, making it difficult to increase the density of semiconductor devices.

By the way, as an MIS type field effect transistor (hereinafter referred to as "MISFET") using poly Si or a high melting point metal as an O ₂ gate electrode, a structure shown in FIG. 1 has been proposed. Reference numeral 1 denotes a substrate, in which a source region 2 and a drain region 3 are provided, and a gate electrode 5 made of polySi or a high melting point metal is provided on the substrate 1 with a gate oxide film 4 interposed therebetween. There is. and gate electrode 5
A CVDSiO ₂ 6 for insulation is provided on the surface of the gate electrode 5, and a contact hole 7 is formed in the CVDSiO ₂ 6 and the gate oxide film 4 on both sides of the gate electrode 5, and the source electrode is connected through this contact hole 7. A drain electrode 8 and a drain electrode 9 are provided in contact with the source region 2 and the drain region 3, respectively. In such a structure, the distance x between the side wall of the gate electrode 5 and the contact hole 7 is particularly large when a high melting point metal is used as the gate electrode 5.
It was not possible to shorten the length due to the voltage resistance of CVDSiO ₂ . Furthermore, considering the process for realizing the structure shown in FIG. 1, after forming the source region 2 and drain region 3 in a self-aligned manner with respect to the gate electrode 5 by ion implantation using the gate electrode 5 as a mask, CVDSiO ₂ After that, a contact hole 7 is formed using lithography technology and etching technology. CVDSiO ₂ 6
Since contact holes 7 are formed uniformly on the gate oxide film 4 other than the surface of the gate electrode 5, it becomes necessary to form a contact hole 7, and due to the accuracy limit of the lithography technology used at this time, the distance x is set to 1 μm or less. It was difficult to do so. As described above, with the conventional technology, it has been difficult to manufacture a MISFET with a structure in which the distance x is shortened, and therefore it has been impossible to realize a high-density semiconductor device. Further, in the conventional semiconductor device, it has been difficult to increase the operating speed due to the distance existing between the gate region under the gate electrode 5 and the contact hole 7.

(Object of the Invention) An object of the present invention is to provide a semiconductor device having an electrode/contact hole structure in a self-aligned positional relationship suitable for high density, and a method for manufacturing the same.

Another object of the present invention is to provide a high-speed semiconductor device and a method for manufacturing the same.

Another object of the present invention is to provide a semiconductor device having a highly insulating silicon oxide film only on the surface of an electrode made of a high melting point metal, and a method for manufacturing the same.

Another object of the present invention is to provide a semiconductor device and a method for manufacturing the same with fewer short circuits and disconnections in electrode portions made of high-melting point metal.

Another object of the present invention is to provide a method for manufacturing a semiconductor device using a high melting point metal as an electrode with high yield.

(Structure of the Invention) In order to achieve the above object, a typical semiconductor device according to the present invention includes a high melting point metal layer provided on a substrate having an insulating layer on the substrate, and an internal silicon oxide film. , a silicon layer, the internal silicon oxide film is provided between the high melting point metal layer and the silicon layer, and the internal silicon oxide film is a silicon oxide film formed by internally oxidizing the silicon layer. The silicon layer is in contact with the substrate through a contact hole drilled in the insulating layer, and the contact hole is provided near an end of the high melting point metal layer.

A typical first aspect of the method for manufacturing a semiconductor device according to the present invention includes a step of forming a high melting point metal layer in a predetermined shape on a substrate including an insulating layer; forming a high melting point metal oxide layer on the surface of the high melting point metal oxide layer; forming a contact hole in the insulating layer adjacent to an end of the high melting point metal layer; a step of forming a silicon layer so as to cover the substrate, and heat-treating the substrate having the high melting point metal layer, the high melting point metal oxide layer, and the silicon layer in an atmosphere containing hydrogen, and forming the high melting point metal layer and the silicon layer. The method is characterized in that it includes a step of forming an internal silicon oxide film during the step. Furthermore, according to a second aspect of the manufacturing method, after forming a silicon layer on the contact hole and the high melting point metal oxide layer in the first aspect, the surface of this silicon layer is oxidized, and then an internal silicon oxide film forming step is performed. It is characterized by doing the following. Further, according to third and fourth aspects of the manufacturing method, the order of the high melting point metal oxide forming step and the contact hole forming step is performed in the reverse order in the first and second aspects, respectively. .

(Example) The present invention will be explained below based on examples.

FIG. 2 shows an embodiment in which the present invention is applied to a MISFET. 11 is, for example, P with a specific resistance of about 3 Ωcm.
Type single crystal substrates 12 and 13 are source and drain regions provided in the substrates, respectively, and have a surface concentration of n-type impurities of, for example, 2×10 ²⁰ cm ⁻⁸ and a depth of 0.25 μm. A high melting point metal layer with a thickness of 0.3 μm, for example, is formed on the substrate 11 with a gate oxide film 14 interposed therebetween.
A gate electrode 15 made of Mo is provided, and this gate electrode 15 has a predetermined shape, for example, a rectangular cross-sectional shape. 16 is an internal silicon oxide film with a thickness of, for example, 700 Å, which is formed by oxidizing the silicon layer constituting the source and drain electrodes from the inside, that is, from the high melting point metal layer side that is the gate electrode 15; This contact hole 17 is provided at a self-aligned position with respect to the gate electrode 15 through the internal silicon oxide film 16 near the end of the gate electrode 15, and through this contact hole 17, the A source electrode 18 and a drain electrode 1 consisting of
9 are provided so as to be in contact with the source region 12 and the drain region 13, respectively. Source electrode 1
8 and the silicon layer constituting the drain electrode 19 are
It may be poly Si or amorphous silicon, and the thickness is, for example, 0.35 μm, and the impurity concentration is about 10 ²¹
cm ^-3 .

In such a MISFET, the gate electrode 15 and the contact hole 17 are provided in a self-aligned positional relationship through a thin internal silicon oxide film 16 with a thickness of y that is selectively formed only on the surface of the gate electrode 15. Therefore, the size of the device is smaller than when CVDSiO ₂ is used, making it a structure suitable for high density.

Furthermore, the distance y between the gate region and the contact hole
Since the length can be shortened, the operating speed of the semiconductor device can be further increased.

Further, as described later, the internal silicon oxide film 16 has the same film quality as a silicon thermal oxide film, for example, has a dielectric strength, so the MISFET according to the present invention
can improve the insulation properties between the gate electrode 15 and the source electrode 18 (or drain electrode 19).

FIG. 3 shows an example in which the present invention is applied to a semiconductor device having a so-called two-layer gate structure. 20 is provided on the gate oxide film 14
A cell plate electrode made of poly Si, 21 is a silicon oxide film with a thickness of 0.1 μm formed by oxidizing poly Si on the cell plate electrode 20, and a gate electrode 15 made of a high melting point metal layer is a gate oxide film. 14 and a part of the silicon oxide film 21, an internal silicon oxide film 16 is provided on the surface of the gate electrode 15, and a contact part 22 covers a part of this internal silicon oxide film 16. This is a silicon layer provided so as to be in contact with a region 24 in the substrate 11 through a hole 23. The above-mentioned cell plate electrode 20 is used as an electrode for the capacitor portion. In the semiconductor device having this structure, the contact hole 23 is provided in a self-aligned positional relationship with the gate electrode 15 through the internal silicon oxide film 16, similar to the one in FIG. However, the number of contact holes is one for one gate electrode.

Next, another embodiment in which one contact hole is provided for one gate electrode is shown in FIGS. 4 and 5.

In FIG. 4, reference numeral 15 denotes a gate electrode provided on the substrate 11 via a gate oxide film 14. An internal silicon oxide film 16 is provided on the surface of the gate electrode 15, and one end of the gate electrode 15 is provided with an internal silicon oxide film 16. The silicon layer 22 is in contact with a region 24 in the substrate 11 through a contact hole 23 provided in a self-aligned position with respect to the gate electrode 15 through the internal silicon oxide film 16 near the portion of the gate electrode 15 .
There is a cell plate electrode 25 provided on the gate oxide film 14 through the internal silicon oxide film 16 near the end of the value of .
is composed of another silicon layer that is insulated and separated from the silicon layer 22.

In FIG. 5, a gate oxide film 1 on a substrate 11 is shown.
One of the two high melting point metal layers provided through the gate electrode 4 is used as the gate electrode 15 and the other as the cell plate electrode 26, and the internal silicon oxide film 1 is formed on the surfaces of the gate electrode 15 and the cell plate electrode 26.
6 is provided, and a silicon layer 22 is provided so as to cover the internal silicon oxide film 16 and the gate oxide film 14.
This silicon layer 22 connects to a region 24 in the substrate 11 at one end of the gate electrode 15 through a contact hole 23 located in a self-aligned position via the internal silicon oxide film 16.
Another region 27 is provided in the substrate 11 that is in contact with the cell plate electrode 26 and corresponds to the gap between the other end of the gate electrode 15 and the cell plate electrode 26 . The silicon layer 22 serves as a gate electrode 15 and a cell plate electrode 26.
It is not necessary to cover both regions, and it is sufficient that the region 24 is in contact with the region 24 through the contact hole 23.

In the embodiment shown in FIGS. 3 to 5 described above, the substrate 11, the regions 24, 27, and the silicon layers 22, 25 are the same as the substrate 11 of the embodiment shown in FIG.
regions 12 and 13, and silicon layers 18 and 19;
The same thing can be used for each. Also, Figure 3~
In both the structures shown in FIG.
6 is provided, and no internal silicon oxide film 16 is formed on the surface of other portions. Figure 3~
In the semiconductor device having the structure shown in FIG. 5, the gate electrode 15 and the contact hole 23 are in a self-aligned positional relationship through the thin internal silicon oxide film 16, so that the semiconductor device is suitable for increasing the density of integrated circuits. .
Furthermore, since the distance between the gate region and the contact hole is shortened, the semiconductor device can be highly integrated and operate at high speed.

Although FIGS. 2 to 5 illustrate structures in which the silicon layers 18, 19, 20, and 25 are exposed to make the explanation easier to understand, if necessary, an insulating film, wiring layer, etc. may be formed on these structures. Needless to say, it is provided.

Next, one embodiment of the method for manufacturing a semiconductor device according to the present invention will be described.

For example, a silicon oxide film with a thickness of 400 Å is formed on the p-type single crystal silicon substrate 11 as an insulating layer to be used as the gate oxide film 14, and then a high melting point metal layer is formed, and this high melting point metal layer is formed using a known lithography technique. Gate electrode 1 is processed using etching technology.
5 to obtain the structure shown in FIG. 6-A. The material used for the high melting point metal layer of the gate electrode 15 must have low resistivity, high heat resistance, and the oxide of the material must be easily reduced by heat treatment in an atmosphere containing hydrogen. Yes, for example
There are Mo, W, Ta, Ti, etc. In this example, the following
This will be explained in detail using Mo as an example. The gate electrode 15 in FIG. 6-A is made of Mo with a thickness of about 3000 Å formed by electron beam evaporation.

Next, an n-type impurity such as arsenic is applied to the structure shown in Fig. 6-A from the main surface 30 side at a dose of 4×10 ¹⁵ cm.
^-2 , ions are implanted with an implantation energy of 100 keV using the gate electrode 15 as a mask, and then annealing is performed to form a source region 12 and a drain region 13.
- Obtain the structure of diagram B.

Next, the surface of the high melting point metal layer used as the gate electrode 15 is oxidized to form a high melting point metal oxide layer 31 to obtain the structure shown in FIG. 6-C. Generally obtained stably when Mo is used as the high melting point metal layer 4.
Mo oxides include molybdenum dioxide (hereinafter referred to as " _MoO2 ") and molybdenum trioxide (hereinafter referred to as " _MoO3 "). MoO ₃ can be easily obtained by heat-treating Mo at a low temperature in an oxygen-containing atmosphere, but this MoO ₃ begins to sublimate at high temperatures of about 800°C or higher. For this reason, when MoO ₃ is used as the high melting point metal oxide layer 31, the heat treatment described later may cause peeling of MoO ₃ , which is disadvantageous. Therefore, as the high melting point metal oxide layer 31, it is necessary to use MoO ₂ , which has a high melting point of 1900° C. and is stable at high temperatures. However, conventionally it has not been easy to form MoO ₂ on the Mo surface. As a result of various studies, we have discovered two methods of oxidizing Mo that can stably produce MoO ₂ on the Mo surface. The first method is to oxidize Mo at about 300°C in an oxygen atmosphere, and once the surface of Mo is
MoO ₃ is formed, followed by heat treatment in an inert gas (e.g. nitrogen gas) at a temperature close to or above the sublimation point of MoO ₃ to convert MoO ₃ to MoO ₂ and form MoO ₂ on the surface of Mo. It's a method. The second method is to heat-treat Mo at a temperature close to or higher than the sublimation point of MoO ₃ in an inert gas (e.g. nitrogen gas) atmosphere containing a trace amount of oxygen (1.0% or less).
This method forms MoO ₂ on the surface. It was confirmed by X-ray diffraction and electron beam diffraction that the Mo oxide on the Mo surface obtained by these two methods was MoO ₂ .
In this example, MoO ₂ which becomes the high melting point metal oxide layer 31 was formed using the first method. As an example, a substrate with Mo is placed in an oxidizing atmosphere.
MoO ₃ was formed on Mo by heat treatment at a temperature of 300°C for 60 minutes, and then heat treatment was performed at a temperature of 800°C for 30 minutes in a nitrogen atmosphere to form MoO ₂ with a thickness of about 400 Å on the surface of Mo. Figure 7 shows the relationship between the thickness of the MoO ₃ film formed on Mo and the formation time, curves a and
The formation temperatures of b and c are 300℃, 320℃, and 350℃, respectively.
This is the dependence of the MoO ₃ film thickness on the formation time in the case of °C. The thickness of the internal silicon oxide film 16 formed as described later is obtained by converting MoO ₃
Since it depends on the thickness of MoO ₂ , it is important to accurately control the thickness of MoO ₃ in order to control the thickness of internal silicon oxide film 16 . Figure 7 shows
This shows that if M ₀ O ₃ is formed at a formation temperature of around 300°C, the thickness of the MoO ₃ film can be precisely controlled. Note that when comparing the two methods for forming MoO ₂ described above, the first method is superior in terms of controlling the film thickness of MoO ₂ and preventing oxygen from diffusing into Mo. Diffusion of oxygen into Mo is not very desirable because it causes a large volumetric contraction of Mo in the internal silicon oxide film formation process described later.

Next, using a known lithography technique, the 6th-C
A resist pattern is formed on the structure shown in the figure. This resist pattern 32 is, for example, the 6th-D
As shown in the figure, it has an opening 32a for forming a contact hole, and it is desirable to form a part of the opening 32a so as to overlap the gate electrode 15. In addition, in the conventional manufacturing process, if a resist pattern is used in which the gate electrode 15 and the opening 32a partially overlap, the exposed gate electrode 15 and the contact electrode will be short-circuited in the subsequent process. The opening 32a must be formed at a distance from the gate electrode 15, and the distance is usually 1 μm or more, taking into account margins in the lithography process and the amount of side etching during etching. . In the present invention, as described later, the silicon layer 33 and the substrate 1
After making the connection with 1, the internal silicon oxide film 16
Since the gate electrode 15 and the silicon layer 33 are insulated and separated by forming the gate electrode 15
A resist pattern may be formed in which the opening 32a and the opening 32a partially overlap.

Next, the gate oxide film 1 of the structure shown in FIG. 6-D
4 is drilled by a known etching technique using the resist pattern 32 as a mask to form a contact hole 17, and then the resist pattern 32 is removed to obtain the structure shown in FIG. 6-E.

Next, a silicon layer 33 is formed on the structure shown in FIG. 6-E to obtain the structure shown in FIG. 6-F. The silicon layer 33 may be made of poly Si or amorphous silicon. In this example, electron beam evaporation was used.
Poly Si was formed to a thickness of 3500 Å. Then this
Impurities such as arsenic are added to lower the resistance of polySi.
It was added to polySi by ion implantation. Other formation methods such as CVD may be used to form the polySi used as the silicon layer 33, and impurities may be added at the time of formation. Furthermore, it goes without saying that the impurity concentration of polySi may be appropriately set depending on the use of polySi.

Next, the structure shown in FIG. 6-F is heat-treated in a hydrogen atmosphere or an inert gas (for example, nitrogen gas) atmosphere containing hydrogen to reduce the high melting point metal oxide layer 31 and at the same time remove the internal silicon layer 33. , that is, the internal silicon oxide film 1 is oxidized from the high melting point metal layer side.
6 to obtain the structure shown in FIG. 6-G. In this example, a heat treatment was performed at a temperature of 1000° C. for 60 minutes in a hydrogen atmosphere to reduce MoO ₂ to Mo, and at the same time, an internal silicon oxide film 16 was formed to a thickness of about 700 Å. In the above example, heat treatment is performed at 1000°C for 60 minutes, but this heat treatment condition is such that the high melting point metal oxide layer 31
It is sufficient that the silicon layer 33 is oxidized from inside at the same time as the reduction of the heat treatment temperature, and the heat treatment temperature may be about 800°C. It is also possible to turn the internal silicon oxide film 16 into phosphorus glass by adding phosphine (PH ₃ ) to the heat treatment atmosphere.

Next, a part of the silicon layer 33 on the gate electrode 15 is removed using known lithography and etching techniques, and the remaining silicon layer is used as the source electrode 18 and the drain electrode 19 to obtain the structure shown in FIG. 6-H. . In this case, an insulating film such as a silicon oxide film formed by oxidizing the silicon layer 33 may be provided in the gap between the source electrode 8 and the drain electrode 19.

After this, steps for forming interlayer insulating films, wiring layers, etc. may be performed as necessary.

The changes in the structure before and after the above-mentioned internal silicon oxide film forming step will be explained based on the measurement results of Auger electron spectroscopy shown in FIG. 8A shows the structure before forming the internal silicon oxide film, that is, the structure shown in FIG. 6-F, and FIG. 8B shows the structure after the internal silicon oxide film formation process, that is, the structure shown in FIG. The depthwise distribution of constituent elements in 11 directions is shown. The horizontal axis represents the time during which the sample was sputter etched, which corresponds to the depth from the surface of the silicon layer 33. a, b, and c are curves representing silicon, oxygen, and Mo, respectively.

FIG. 8A clearly shows that MoO ₂ is formed on Mo and poly Si is further formed on MoO ₂ . Comparing Figure 8B with Figure 8A, the part that was MoO ₂ is reduced to Mo and becomes poly
It can be seen that an internal silicon oxide film of approximately 700 Å is formed from the vicinity of the interface between Si and MoO ₂ toward the polySi surface.

According to FIG. 8B, there is no oxygen in Mo, and in the internal silicon oxide film formation process described above.
This shows that Mo is not oxidized, and Mo
This shows that no silicide is formed due to the reaction between silicon and silicon. Furthermore, from FIG. 8B, the interface between poly Si and the internal silicon oxide film and the interface between the internal silicon oxide film and Mo both show a very steep Auger electron distribution, so both interfaces are very homogeneous and It is determined that they are uniformly formed. The reason why the internal silicon oxide film 16 shown in FIG. 6-G is formed by heat-treating the structure shown in FIG. 6-F in an atmosphere containing hydrogen is considered to be as follows.

That is, MoO ₂ is reduced by the following reaction, MoO ₂ +2H ₂ →Mo+2H ₂ O The H ₂ O generated at this time reduces the silicon layer 3.
It is considered that the poly Si, which is No. 3, is oxidized and an internal silicon oxide film 16 is formed. Therefore, the amount of hydrogen used as the heat treatment atmosphere should be sufficient to be used in the above-mentioned reduction reaction. Since the amount of H ₂ O generated in the above reduction reaction is limited by the amount of oxygen constituting MoO ₂ , the maximum thickness of the internal silicon oxide film 16 that can be formed is the thickness of MoO ₂ . It should be noted that it is determined by

Next, the quality of the internal silicon oxide film 16 formed in the internal silicon oxide film forming step described above was evaluated using various methods, and the results will be explained. First of all
When the composition of the internal silicon oxide film 16 was examined by XPS (X _{-ray phptpelectrpo spectrpscppy} ) measurement, the binding energy of the 2p electrons of silicon in this film was 103.3eV, which is the same as that of the 2p electrons of silicon in a normal silicon thermal oxide film. Since the binding energy value almost matched 103.4 eV, the internal silicon oxide film 16
It was determined that the composition was similar to that of a normal silicon thermal oxide film. Next, the internal silicon oxide film 16
The etching rate for dilute hydrofluoric acid (hydrofluoric acid:water = 3:100) is 120 Å/min, and the etching rate for a normal silicon thermal oxide film with a similar solution is 109
It was almost equivalent to Å/min. Next, a 500 μ square poly Si-Al2 layer electrode was formed on the internal silicon oxide film 16, and the breakdown voltage and leakage current of the internal silicon oxide film 16 were measured, and the breakdown voltage was 10 ⁶ V/cm or more.
The leakage current was less than 10 ^-12 A, which is equivalent to that of a normal silicon thermal oxide film. From the results of the above evaluation, it was concluded that the film quality of the internal silicon oxide film 16 was equivalent to that of a normal silicon thermal oxide film.

As explained above, when the method according to the present invention is used, the silicon layer 33 and the gate electrode 15 can be insulated and separated after the silicon layer 33 is formed. Since the contact hole 17 can be formed overlapping the gate electrode 15, the contact hole 17 can be formed in a self-aligned position with respect to the gate electrode 15. As a result, a structure in which the gate electrode 15 and the contact hole 17 are close to each other via the thin internal silicon oxide film 16 is realized, and a semiconductor device having a small area and suitable for increasing the density of integrated circuits can be realized. For example, compared to conventional structures, the distance between the gate electrode and contact hole can be reduced by more than an order of magnitude, and the cell area can be reduced by several tens of percent. Further, since the distance between the gate electrode under the gate electrode 15 and the contact hole 17 is uniquely determined by the thickness y of the internal silicon oxide film 16, and this distance is short, an extremely high-speed semiconductor device can be realized.

Furthermore, as explained in FIG. 8, the quality of the internal silicon oxide film is similar to that of silicon thermal oxide film and is superior to CVDSiO ₂ . A semiconductor device with good insulation properties between silicon layers used as a semiconductor layer can be realized. Furthermore, the internal silicon oxide film 16 is
H ₂ O generated when reducing the high melting point metal oxide layer that is evenly and uniformly formed on the surface of the high melting point metal layer.
Since the metal layer is formed using the same method, it has a structure that uniformly and selectively covers only the surface of the high melting point metal layer. Therefore, a short circuit is unlikely to occur between the gate electrode 15 and the source electrode 18 and drain electrode 19, and the internal silicon oxide film 16 is formed at the stepped portion of the gate electrode 15.
Since the silicon layer is not formed in an overhang shape, disconnection of the silicon layer at the stepped portion does not become a problem. Since there are no short circuits or disconnections, the manufacturing yield is also extremely high. Furthermore, in the internal silicon oxide film formation process, conventional
In order to prevent the formation of MoO ₃ as in the case of forming CVDSiO ₂ , it is possible to easily form the internal silicon oxide film 1 on the gate electrode 15 without requiring complicated procedures and time.
6 can be formed.

In addition, since MoO ₂ of the high melting point metal oxide layer 31 can be relatively resistant to acid cleaning, the element can be cleaned by performing appropriate acid cleaning in the process from FIG. 6-D to FIG. 6-E. The surface of the product can be cleaned, improving manufacturing yield and preventing contamination of manufacturing equipment.

The manufacturing method described above is not limited to the steps shown in FIGS. 6-A to 6-G, and various modifications can be considered.

As a first modification, the ion implantation step and the refractory metal oxide layer forming step are reversed in the embodiment shown in FIG. That is, the structure shown in FIG. 6-A is subjected to a high melting point metal oxide layer forming step to obtain the structure shown in FIG. By doing so, the structure shown in Figure 9-B is obtained, and then the structure shown in Figure 6
By the same process as in the case of Fig. 6-D to Fig. 6-
Obtain the structure of diagram H. According to this method, a high melting point metal oxide layer 31 with poor crystallinity is formed on the surface of the gate electrode 15.
, the blocking ability against ion implantation can be increased, which is effective in improving the so-called channeling phenomenon. For example, it is particularly effective when the gate electrode 15 is made of a film with better crystallinity or a thinner film of 2000 Å or less, such as Mo.

In a second modification, the high melting point metal oxide layer forming step and the contact hole forming step are reversed. That is, using the structure of FIG. 6-B, the same steps as those used to obtain the structures of FIGS. 6-D and 6-E are performed to obtain the structures of FIGS. 10-A and 10-B, Next, a high melting point metal oxide layer forming step is performed to obtain the structure shown in FIG. 10-C. In this case, a part of the substrate 11 exposed through the contact hole 17 is also oxidized when forming the high melting point metal oxide layer, but since the oxidation temperature at this time is as low as about 300°C, the silicon oxide formed on the substrate 11 is Since the film has a thickness comparable to that of the natural oxide film of silicon, the structure shown in Figure 10-C can be realized without substantially reducing the thickness of the gate oxide film 14 by performing a light etching process using dilute hydrofluoric acid. . In addition,
MoO ₂ is sufficiently resistant to dilute hydrofluoric acid. Thereafter, the same structure as shown in FIGS. 6-F to 6-H is obtained by the same steps as in FIG. 6.

By the way, in the embodiments of the manufacturing method described so far, if the polySi used as the silicon layer 33 is thin (for example, about 1500 Å), it becomes difficult to form a rather thick internal silicon oxide film at the interface between Mo and polySi. The reason for this is thought to be that if the silicon layer 33 is too thin, H ₂ O will dissipate to the outside through pinholes and grain boundaries in the silicon layer 33 during formation of the internal silicon oxide film. In order to solve this problem, after obtaining the structure shown in Fig. 6-F, obtain the structure shown in Fig. 11-A in which a silicon oxide film 34 is formed on the surface of the silicon layer 33, and then obtain the structure shown in Fig. 6-G. The 11th-B structure may be obtained by performing a process for obtaining the structure. Thereafter, this silicon oxide film 34 may be left and used or removed as required.

FIG. 12 shows the results of Auger electron spectroscopy when the internal silicon oxide film 16 is formed using the structure shown in FIG. 11-A in comparison with the case where the silicon oxide film 34 is not provided. The silicon layer 33 is made of poly with a thickness of 1100 Å formed by electron beam evaporation method.
Using Si, the silicon oxide film 34 was made, for example, by thermally oxidizing the silicon layer 33 to a thickness of 400 Å. 12th
Figure A shows the case where the internal silicon oxide film is formed without providing the silicon oxide film 34, and Figure 12B shows the case where the internal silicon oxide film is formed with the silicon oxide film 34 provided, from the surface of the silicon layer 33. The depthwise distribution of the constituent elements in the direction of the substrate 11 is shown. When there is a silicon oxide film 34, as shown in FIG. 12B, a relatively thick internal silicon oxide film 16 is formed between poly Si and Mo, and the interface between poly Si and internal silicon oxide film 16 and the internal silicon oxide film are It can be seen that both the interfaces between No. 16 and Mo are formed homogeneously and uniformly. It has also been confirmed that even if the silicon oxide film 34 is formed by thermally oxidizing polySi, Mo is not oxidized.

On the other hand, as a countermeasure when the silicon layer 33 is thin, it is effective to make the surface of the silicon layer ₃₃ amorphous or cover it with a dense film. The surface may be directly nitrided.

The method for manufacturing a semiconductor device having two contact holes for one gate electrode has been described above. Next, a method for manufacturing a semiconductor device having one contact hole for one gate electrode will be briefly described.

Polymer film, which will become the cell plate electrode 20, is placed on the p-type single crystal silicon substrate 11 via the gate oxide film 14.
Si is formed and processed, an insulating layer such as a silicon oxide film 21 is formed on its surface, and a gate oxide film 1 is further formed.
4 and the silicon oxide film 21, and this high melting point metal layer is processed into a predetermined shape so as to overlap at the stepped portion of the cell plate electrode 20 to form the gate electrode 15, as shown in FIG. 13-A. obtain the structure of Thereafter, the same steps as those for obtaining the structures shown in FIGS. 6-B to 6-G are performed, respectively, to obtain the structures shown in FIGS. 13-B to 13-B.
The structure shown in Figure 13-G is obtained. The difference from the series of FIGS. 6 is that only one impurity region 24 is provided in the substrate by ion implantation (FIG. 13-B).
The number of contact holes 23 is also one for the gate electrode 1
There is only one point compared to 5. Thereafter, the silicon layer 22 is processed as necessary to obtain the structure shown in FIG. 13-H.

Next, another embodiment of the manufacturing method in which there is only one contact hole will be described. The structure shown in Fig. 14-A (same as that shown in Fig. 6-A) was subjected to the same high melting point metal oxide layer forming process as in obtaining the structure shown in Fig. 6-C, and the structure shown in Fig. 14-B was Get structure. Next, the sixth
The same steps as those used to obtain the structures shown in Figs. -D to 6-F are performed to obtain the structures shown in Figs. 14-C to 14-E. At this time, one contact hole 23 is formed for each gate electrode 15.

Next, the structure shown in FIG. 14-E is heat-treated in an inert atmosphere (for example, nitrogen) to diffuse the impurities in the silicon layer 22 into the substrate 11 and form the impurity concentration region 2.
4 to obtain the structure shown in FIG. 14-F. Thereafter, the same steps as those used to obtain the structures shown in FIGS. 6-G and 6-H are performed to obtain the structures shown in FIGS. 14-G and 14-H. At this time, a part of the silicon layer 22 is used as the cell plate electrode 25. Furthermore, the 14th-
The process of obtaining the structure shown in Figure F and the process of obtaining the structure shown in Figure 14-G may be reversed.

Next, another embodiment of the manufacturing method in which there is only one contact hole will be described. First, a high melting point metal layer which will become the gate electrode 15 and the cell plate electrode 26 is formed on the substrate 11 as shown in FIG. 15-A through the gate oxide film 14, and then, as shown in FIGS. 6-B to 6-G. The structures shown in FIGS. 15-B to 15-G are obtained by the same process as in obtaining . At this time, the difference from the series of cases shown in FIG. 6 is that the contact hole 23 is provided only near the end of the gate electrode 15 on the opposite side from the cell plate electrode 26.
Through this contact hole 23, the silicon layer 2
2 is connected to one impurity region 24. Thereafter, the silicon layer 22 may be processed if necessary.

9-A to 9-B and 10-A to 10-C in the embodiments of FIGS. 13-A to 13-H and 15-A and 15-H. and the first
Modifications such as those shown in Figures 1-A to 11-B are possible, and even in the embodiments shown in Figures 14-A to 14-H, modifications such as those shown in Figures 10-A to 10-C and 11- A
Modifications as shown in Figures to Figures 11-B are possible.

The present invention is not limited to the embodiments described above; for example, when forming an internal silicon oxide film,
Instead of reducing all MoO ₂ , a portion of MoO ₂ may be reduced and the silicon layer may be oxidized at the same time to form an internal silicon oxide film. Further, an n-type single crystal silicon substrate is used as the substrate 11, and regions 12, 1
P-type impurities may be introduced into 3, 24, and 27, and various combinations are also possible depending on other elements. Further, impurities may be introduced into the substrate 11 to form the regions 12, 13, 24 by utilizing impurity diffusion from the silicon layers 18, 19, 22, 23, etc., as shown in FIG. 14-F. Furthermore, only the silicon layer separated from the refractory metal layer by the internal silicon oxide film may be removed, and another conductive layer having a lower resistance may be provided in the exposed area of the silicon layer. Also, the explanation so far has focused on MISFET,
It goes without saying that the present invention is not necessarily limited to MISFETs, but is a technology that can be widely applied to semiconductor devices in which the positions between electrode wirings or between electrode wirings and contact holes need to be formed in a self-aligned manner. There is no such thing. In addition, in the example
Although the present invention has been explained using Mo, it is sufficient that the high melting point metal oxide can be reduced by heat treatment in an atmosphere containing hydrogen, and it is clear that most high melting point metals are applicable to the present invention. Further, if the manufacturing process does not include a high-temperature step, a metal having the above-mentioned properties and having a melting point lower than the high-melting point metal may be used instead of the high-melting point metal layer.

(Effects of the Invention) As described above, by using the present invention, it is possible to selectively form an internal silicon oxide film of the same quality as a normal silicon thermal oxide film only on the surface of a high melting point metal layer. In connection with this, various other effects can be obtained as follows.

(1) Gate electrodes and contact holes can be formed in a self-aligned positional relationship through the internal silicon oxide film, making it possible to realize a semiconductor device suitable for increasing the density of integrated circuits.

(2) Since the distance between the gate electrode and the contact hole can be determined only by the thickness of the thin internal silicon oxide film, a high-speed semiconductor device can be realized.

(3) Since the internal silicon oxide film has good insulation properties, a semiconductor device with excellent insulation properties between the gate electrode and the silicon layer can be realized.

(4) The internal silicon oxide film is formed by uniformly oxidizing the silicon layer after covering the gate electrode, so there is no short circuit between the gate electrode and the silicon layer, and there is no disconnection in the silicon layer. Semiconductor devices can be manufactured with high yield.

(5) Since the internal silicon oxide film or high melting point metal oxide layer is resistant to acid cleaning, the element surface can be easily cleaned by acid cleaning during the manufacturing process, improving manufacturing yield and improving manufacturing equipment. can reduce pollution.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a conventional MISFET, and FIG. 2 is a cross-sectional view of a MISFET that is an embodiment of the present invention.
3 to 5 are cross-sectional views of a semiconductor device according to another embodiment of the present invention, and FIGS. 6-A to 6-H are sectional views of a semiconductor device according to another embodiment of the present invention.
Figure 7 for explaining the manufacturing method of the semiconductor device shown in Figure 7.
The figure shows the dependence of the MoO ₃ film thickness on the formation time.
12 and 12 are diagrams showing the depth distribution of constituent elements determined by Auger electron spectroscopy of a semiconductor device manufactured by the method according to the present invention, FIG. 9-A, and FIG.
Figure -B, Figure 10-A to Figure 10-C, Figure 11-
FIG. A and FIG. 11-B are diagrams for explaining a modification of the manufacturing method of the semiconductor device in FIG. 2, and FIG. 13-A to
Figure 13-H, Figure 14-A to Figure 14-H, and Figure 15-A to Figure 15-G are Figure 3, respectively.
FIG. 6 is a diagram for explaining a method for manufacturing the semiconductor device shown in FIGS. 4 and 5. FIG. 1, 11...substrate, 2, 12... source region,
3,13...Drain region, 4,14...Gate oxide film, 5,15...Gate electrode, 6...
CVDSiO ₂ , 7, 17, 23... contact hole, 8, 18... source electrode, 9, 19... drain electrode, 16... internal silicon oxide film, 20,
25, 26... Cell plate electrode, 22, 33...
...Silicon layer, 24, 27...Region, 30...Main surface, 31...High melting point metal oxide layer, 32...Resist pattern, 32a...Opening for contact hole formation, 34...Silicon oxide film.

Claims (1)

[Scope of Claims] 1. A step of forming a high melting point metal layer in a predetermined shape on a substrate via an insulating layer; a step of oxidizing the surface of the high melting point metal layer to form a high melting point metal oxide layer; forming a contact hole in the insulating layer adjacent to an end of the high melting point metal layer; forming a silicon layer to cover the contact hole and the high melting point metal oxide layer; and forming a silicon layer in the high melting point metal layer. , comprising the step of heat-treating the substrate having the high melting point metal oxide layer and the silicon layer in an atmosphere containing hydrogen to form an internal silicon oxide film between the high melting point metal layer and the silicon layer. A method for manufacturing a semiconductor device. 2. A step of forming a high melting point metal layer in a predetermined shape on a substrate via an insulating layer, a step of oxidizing the surface of the high melting point metal layer to form a high melting point metal oxide layer, and a step of forming a high melting point metal layer on the edge of the high melting point metal layer. forming a contact hole in the insulating layer adjacent to the part, forming a silicon layer to cover the contact hole and the high melting point metal oxide layer, and forming a silicon oxide film on the surface of the silicon layer. and a step of heat-treating the substrate having the high melting point metal layer, the high melting point metal oxide layer, the silicon layer, and the silicon oxide film in an atmosphere containing hydrogen to form a space between the high melting point metal layer and the silicon layer. A method for manufacturing a semiconductor device, comprising the step of forming an internal silicon oxide film. 3. forming a high melting point metal layer in a predetermined shape on a substrate via an insulating layer; forming a contact hole in the insulating layer adjacent to an end of the high melting point metal layer; oxidizing the surface to form a high melting point metal oxide layer, forming a silicon layer to cover the contact hole and the high melting point metal oxide layer, the high melting point metal layer and the high melting point metal oxide. producing an internal silicon oxide film between the high melting point metal layer and the silicon layer by heat treating a substrate having a metal layer and the silicon layer in an atmosphere containing hydrogen. Method. 4. Forming a high melting point metal layer in a predetermined shape on a substrate via an insulating layer, forming a contact hole in the insulating layer adjacent to an end of the high melting point metal layer, and forming a high melting point metal layer on the substrate. oxidizing the surface to form a high melting point metal oxide layer, forming a silicon layer to cover the contact hole and the high melting point metal oxide layer, and forming a silicon oxide film on the surface of the silicon layer. a step of heat-treating the substrate having the high melting point metal layer, the high melting point metal oxide layer, the silicon layer, and the silicon oxide film in an atmosphere containing hydrogen to form a space between the high melting point metal layer and the silicon layer. A method for manufacturing a semiconductor device, comprising the step of forming an internal silicon oxide film.