JPH0216645A - Abnormality detecting circuit - Google Patents

Abstract

PURPOSE:To detect an abnormal state when no address signal is generated for more than a specific period while a busy signal is generated by accessing a storing section storing data for data after designating an address and generating the busy signal from a control section while the accessing operation is performed. CONSTITUTION:A control section 2 is actuated by a start signal outputted from the detecting section 6 of an abnormality detection circuit and starts time counting on the busy signal timer 6a and address signal timer 6b of the detecting section simultaneously with the output of the start signal. Moreover, the section 2 performs address designation to a storing section 1 and outputs a busy signal to the detecting section 6 upon receiving the start signal. During a normal operation, the section 2 inputs an address signal 5 to the detecting section 6 before the timer 6b completes the time counting operation and, as a result, the timer 6b is reset and the section 2 is restarted. When abnormality occurs, the address signal is stopped while the busy signal is generated and the timer 6b completes the time counting and outputs an abnormality detecting signal.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an abnormality detection circuit.

[Prior Art] Currently, voice analysis and synthesis integrated circuits for storing and reproducing arbitrary voice signals are commercially available. In this type of device, in order to detect an abnormality in data access to a storage circuit, the generation time of a busy signal from a control section consisting of a CPU is monitored. In other words, since the recording time is determined by the storage capacity of the storage circuit, if the busy signal continues to be generated for a longer period of time, it is assumed that an abnormality has occurred and an abnormality notification such as a display is performed.

[Problem to be Solved Wi] Since the conventional abnormality detection circuit described above detects only the busy and - signals, the detection time is longer than the access time by the control unit.

Particularly, in the case where the recording time can be changed to multiple stages, the abnormality detection time must be set longer than the maximum recording time, and the abnormality detection takes a long time.

Furthermore, if the recording time is changed, the abnormality detection time must also be changed accordingly.

The main object of the present invention is to provide an abnormality detection circuit that can detect abnormal operation of a control section at an early stage.

[Means for Solving the Problems] The present invention includes a storage section in which data is stored, and a control section that controls access to the data by specifying addresses to the storage section and generates a busy signal during the access. The above-mentioned problem is solved by providing a detection section that detects an abnormal operation when an address signal is not generated for a certain period of time or more while a busy signal is generated from the control section.

[Example] Hereinafter, one embodiment of the present invention will be described based on the drawings.

In FIG. 1, 1 is a storage unit for storing audio data;
Reference numeral 2 denotes a control unit that specifies addresses to the storage unit 1 to control data access and generates a busy signal during this access; 3 a data bus for access to the storage unit 1 by the control unit 2; and 4 An address bus for specifying addresses from the control unit 2 to the storage unit 1; 5 is an address signal generated at regular address value intervals; 6 is the control unit 2;
This is a detection unit that detects abnormal operation. 6a is a busy signal timer that measures a time slightly longer than the maximum recording length;
Reference numeral 6b is an address signal timer that measures a time slightly longer than the generation interval time of the address signal 5 during normal operation.

Next, the operation will be explained along the flowchart of FIG. First, the control section 2 starts operating in response to a start signal output from the detection section 6. The detection section 6 outputs the start signal and at the same time starts clocking the busy signal timer 6a and the address signal timer 6b. The control section 2 specifies an address to the storage section 1 according to the start signal and starts accessing it, and outputs a heavy signal to the detection section 6 (routine ①).

During normal operation, the address signal 5 is input to the detection section 6 before the address signal timer 6b finishes counting, so the address signal timer 6b is reset and restarted (routine 2).

Next, when an abnormality occurs, that is, when the address signal stops even though the busy signal is being generated, the address signal timer 6b stops counting and an abnormality detection signal is generated. (routine ■).

Next, even if the busy signal timer 6a finishes counting while the control unit 6 is generating a busy signal, the detection unit 6 detects the abnormality as the control unit 2 is operating abnormally (routine ■).

If the generation of the busy signal ends before the busy signal timer 6a finishes counting, it is normal operation (routine ■).
.

In addition, when an abnormal operation is detected by the detection section 6, measures such as notifying the abnormality through a display or an alarm sound or resetting the control section 2 are taken.

By the above-described operation, abnormal operation of the control section 2 can be detected at an earlier stage.

In this example, a voice analysis and synthesis circuit is used as an example, but the present invention is not limited to this, and any circuit that accesses data in a storage unit may be used.

[Effects] According to the present invention, abnormal operation of the control section can be quickly detected by checking the progress of the addressing operation for the storage section of the control section using the address signal. There is no time wastage and you can take action quickly. Furthermore, even if the processing operation time of the control unit is lengthened by adding memory, the change frequency of the address line remains the same, so there is no need to change the abnormality detection time, making it easy to accommodate such memory additions. Able to adapt.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a flowchart for explaining the operation of the block diagram in FIG. 1...Storage unit 2...Control unit 3...Detection unit and above Applicant Seikosha Co., Ltd.

Claims (1)

[Scope of Claims] A storage section in which data is stored, and a device that controls access to data by specifying an address to this storage section and that is busy during this access.
) signal, and a detection section that detects an abnormal operation when an address signal is not generated for a certain period of time while a busy signal is being generated from the control section. Abnormality detection circuit.