JPH05197620A - Address space expansion method - Google Patents

Abstract

(57) [Abstract] [Purpose] The expansion of the address space directly accessible from the CPU is enabled by partial modification without affecting the entire system. [Constitution] The conventional one bus is divided into two, the address space of only one bus is expanded, and the connection / disconnection control of the two buses and the conversion of the upper address are performed. By expanding the address space, it is possible to add memory with a larger capacity than when adding expansion memory, and since the specifications of the conventional external slot can be retained, options that can be connected to the external slot of the old model are available. Can be used as is.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention, in an information processing apparatus for designating a device such as a memory by an address via an internal bus, partially expands the address space in the same system in order to add the memory. Address space extension method.

[0002]

2. Description of the Related Art FIG. 5 shows a configuration of a conventional technique. An information processing apparatus is a CPU 501 and a memory 5 of a central processing unit.
02, a peripheral device interface 504, a DMA controller 505 (here, DMA is Direct Memory Access), an external slot 506, and the like. The external slot 506 is connected by a common bus line, and an address bus 510 and a control signal are connected. 512 is commonly connected to all devices. When the CPU 501 and the DMA controller 505 access the memory 502 or the peripheral device interface 504, a device is designated by the address bus 510, so that a common address space is provided as a device designation device. In order to increase the memory capacity beyond the capacity that can be specified in this address space, it is necessary to add an address signal to expand the address space. However, in the conventional block configuration, when the address space is expanded, the address bus 510 is added, and the 501 connected to the expanded bus is added.
It was necessary to modify all the devices from No. 505 to 505, and it could not be easily changed because it affects the whole system.

In order to increase the memory capacity, as shown in FIG. 2 of Japanese Patent Laid-Open No. 57-30060, there are 24 and 25 registers inside the memory package 23, and a part of the data is stored in the memory address. However, it is necessary to set a new register by an I / O instruction or the like when the address space inside the memory package 23 is expanded and the CPU accesses it. In the configuration, the address space that can be directly accessed by the CPU is not expanded, and when the memory is expanded by the DMA, there is a problem that it cannot be expanded because there is no function to newly set the register.

[0004]

According to such a conventional technique, it is necessary to change all the devices connected to the common bus in order to expand the address space. Even if all the devices are changed, the bus is not changed. For options such as peripheral devices connected via the external slot 506, the specifications of the external slot 506 must be changed by increasing the signal of the address bus 510. Even if a structural problem such as the number of terminals is solved by the addition of, the expanded address information is not transmitted to the external slot 506, so that a wraparound phenomenon in which an image repeatedly appears in the address space occurs. However, there is a problem that options cannot be used as they are.

Further, when partial address extension is performed, since one system has address spaces of different sizes, the first bus having a wide address space is changed to the second address having a narrow address space. When accessing the second bus, since the upper address information in the first bus is not transmitted through the second bus, a wraparound phenomenon occurs in which the image of the lower address appears in the upper address, and conversely, the second bus. When accessing the first bus from this bus, there is a problem that the second bus cannot supply the upper address of the first bus.

Further, since the first bus and the second bus have different address space sizes, it is possible to access all devices of the second bus from the first bus, but the second bus can be accessed. There is a problem that only part of the first bus can be accessed from the bus. An object of the present invention is to expand the address space that can be easily accessed directly by the CPU or DMA while maintaining compatibility with the conventional circuit as shown in (Embodiment 1). Another purpose is to switch the allocation of the address space so that all devices can access each other between buses having different address sizes as shown in (Embodiment 2).

[0007]

SUMMARY OF THE INVENTION The present invention has a common address bus for designating devices such as memory or I / O and has an expanded address space for increasing memory capacity within a system. And a second bus having a narrower address space than the first bus that is not expanded.
Is allocated to the lowest address space of the first bus, and the first bus and the second bus are connected for access to the address space common to the first and second buses. Mutual access is permitted, and in the access to the address space allocated only to the first bus, the control of the first and second buses is separated so that the second bus is not affected. The bus master is characterized by increasing the address space of one bus, and further has a register for storing an upper address of an address assigned to the first bus, and the bus master connected to the second bus is the first bus. When the device connected to the second bus is accessed, the contents of the register are used to supplement the high-order address so that the second bus is connected to the first bus.
It is characterized in that it can be assigned to different address spaces of the bus.

[0008]

In the first and second buses, the respective address spaces are made to have reciprocity and expandability, and buses of different sizes are separated via a buffer. As a result, the address space can be expanded with a partial modification, and when expanding the expansion memory, it is possible to expand the memory with a larger capacity, and the existing external slot specifications can be taken over. An information processing mechanism can be obtained in which the options connected to the external slot of the model can be used as they are.

[0009]

【Example】

(Embodiment 1) FIG. 1 is a block diagram of an embodiment corresponding to (claim 1), and FIG. 2 is an address map at that time.
The CPU (Central Processing Unit) 101 and the memory 102 are
An address space 202 obtained by the address bus 112,
Addresses by a common address space 201 obtained by the common address bus 110 and an extended address space 203 obtained by adding the extended address bus 111, which are connected to the first bus composed of the common address bus 110 and the extended address bus 111 Have a space. Here, when the address map when the common address bus 110 is 24 bits and the extension address bus 111 is 2 bits,
It shows that the common address space is expanded to 64 MBytes by adding an address expanded to 16 MBytes. The peripheral device interface 104, the DMA controller 105, and the external slot 106 are connected to the second bus addressed only by the common address bus 110, and have the same circuit as in the case where the address is not expanded. In the example, it has an address space of 16 MByte. Although the first bus and the second bus are directly connected by the common address bus 110, the control signal including the command is transmitted to the control signal 112 of the first bus and the second bus.
The bus control signal 113 is separated by a buffer 108 controlled by the bus arbiter 103. The buffer 108 is composed of, for example, a bidirectional gate circuit.

CPU 101 is a peripheral device interface 1
Buffer 1 when accessing a second bus such as 04
08 is opened, the common address space 201 and the address space 202 have the same capacity, and when accessing the extended address space 203 of the memory 102, the buffer 108 is closed to disconnect the second bus, and the image of the second bus is higher. It is prohibited to appear in the address. On the contrary, when accessing the address of the common address space 201 of the memory 102 connected to the first bus by the DMA controller 105 connected to the second bus, the buffer 108 is opened and the buffer 107 is opened. Extension address 111
The address is supplemented by driving the low level to
Access to address space 202 is common address space 2
It becomes access to 01. Further, the control of the buffer 107 is opened at the time of access from the second bus to the first bus, and the control of the buffer 108 can be easily made because it is sufficient to decode the extension address 111 and close it at the time of access to the extension address space 203. Is possible.

In this way, the address space 2 of the second bus is
02 can be treated in the same manner as the common address space 201 of the first bus, and the second bus has a conventional 16 MByte.
Compatible with e-address space, 64M on first bus
The address space can be extended to Byte.

(Embodiment 2) FIG. 3 is a block diagram showing an embodiment of (claim 2), and FIG. 4 is an address map at that time. 301, 302, 303, 304, 30 in FIG.
5, 306, 307, 308, 310, 311, 31
2, 313 are 101, 102, 103, and
104, 105, 106, 107, 108, 110, 1
It corresponds to 11, 112, 113, and register 309
Is a register that holds an extension address when the second bus accesses the first bus. Register 309
IO issued by software means via CPU 301
It is a register that can be set by instructions. In the configuration of FIG. 1, compatibility with the expansion of the second bus is maintained,
Since it is impossible to access the extended address space 103 of the first bus from the second bus, and in this example, DMA transfer to the extended address space 103 cannot be performed, which is a limitation in actual use. turn into. With the configuration shown in FIG. 3, the CPU 301 sets the register 309 so that the extended address 311 at the time of the DMA operation by the DMA controller 305 connected to the second bus.
Can be changed, and the address space 405 of the second bus can be assigned to any of the address spaces 401, 402, 403, and 404 of the first bus on the address map. All addresses on one bus can be accessed.

The DMA controller 305 is a kind of bus master, and the bus master can be replaced with an element having a general CPU function.

[0014]

According to the present invention, it is possible to expand the address space by partial modification while maintaining the compatibility of the past circuits, and further, according to the second embodiment, all the addresses of the buses mutually mutually. Can be accessed and normally operates for application software used without expanding the memory capacity, and normally operates for application software used with the memory capacity expanded.

[Brief description of drawings]

FIG. 1 is a block diagram according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an address map according to the first embodiment of the present invention.

FIG. 3 is a block diagram according to a second embodiment of the present invention.

FIG. 4 is a diagram showing an address map according to a second embodiment of the present invention.

FIG. 5 is a block diagram according to a conventional technique.

[Explanation of symbols]

 101, 301: CPU 102, 302: Memory 103, 303: Bus Arbiter 104, 304: Peripheral Device Interface 105, 305: DMA Controller 106, 306: External Slot 309: Register 110, 310: Common Address Bus 111, 311: Extended Address Bus 112, 312: Address bus 201, 401: Common address space 203, 402, 403, 404: Extended address space 202, 405: Address space

Claims (2)

[Claims] 1. A first bus having a common address bus for designating a device such as a memory or an I / O, and an expanded address space for increasing a memory capacity in one system; In an information processing device including a second bus having an address space narrower than that of the first bus that is not expanded, the second bus is assigned to the lowest address space of the first bus, In the access to the address space common to the second bus, mutual access is permitted by connecting the first bus and the second bus, and the access to the address space allocated only to the first bus is performed. Then, by separating the control of the first and second buses, the address space of the first bus is increased without affecting the second bus. Address space extension method. 2. A bus master having a register for storing a higher-order address of an address assigned to the first bus and connected to the second bus when accessing a device connected to the first bus. 2. The address space expansion system according to claim 1, wherein the second bus can be allocated to a different address space of the first bus by supplementing the upper address with the contents of the register. ..