JPH0216765A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve the reliability and operating speed of the device by providing electrodes and wirings of the same kinds arranged repeatedly at an interval with which electrode contact windows can be formed among those electrodes and wirings. CONSTITUTION:There are formed on a p type silicon semiconductor substrate 1 an n type impurity diffusion region 2, a field insulating film 3, an interlayer insulating film 4, electrodes and wirings 5, 6 as bit lines, and a cover film 7. There are further provided on a word line an edge 13 of the field insulating film 3, an edge 14 of a capacitor lead wire, and an electrode contact window 15 for connecting the n type impurity diffusion layer 2 and the bit line 5. The electrode and wiring 5 as the bit line is formed on a lower layer, while the electrode and wiring 6 as the bit line formed on an upper layer, and the electrodes and wirings 5, 6 are so closely arranged as to be partially overlapped, viewed in a plane. Hereby, a pitch can greatly be reduced while keeping a function as the electrode and wiring, and hence an occupation area can be reduced.

Description

[Detailed Description of the Invention] [Summary] Regarding the improvement of highly integrated semiconductor devices having repetitive patterns such as semiconductor memory devices, the present invention relates to the improvement of highly integrated and high-speed semiconductor devices,
The purpose is to provide a semiconductor device that solves problems such as improving the reliability of electrodes and wiring by simple means. The same type of electrodes/wirings are repeatedly arranged, and the electrodes are formed on the electrodes/wirings with an interlayer insulating film interposed therebetween, and the electrodes are repeatedly arranged so densely that the longitudinal edges of the electrodes/wirings overlap the longitudinal edges of the electrodes/wirings. - Constructed to include electrodes and wiring of the same type as the wiring.

[Industrial application field]

The present invention relates to improvements in highly integrated semiconductor devices having repetitive patterns, such as semiconductor memory devices.

In semiconductor memory devices, as the degree of integration increases, electrodes and interconnections are formed densely, resulting in interconnect pinch, that is, the narrowing of the distance between the center line of one interconnect and the center line of an adjacent interconnect. is needed. However, even if this is done, the reliability of the electrodes and wiring and the high speed of element operation must be maintained.

[Conventional technology]

Conventionally, in a semiconductor memory device, in order to reduce the pitch of the wiring, the width of the wiring and the width between the wirings are also narrowed.

FIG. 11 is a plan view of the main parts for explaining a conventional semiconductor memory device, FIG. 12 is a side view of the main parts cut away along the line Xl-X1 seen in FIG. 11, and FIG. 13 is the same line X2-X2. FIG. 14 shows a cutaway side view of the main part taken along the line Yl-Yl, respectively. Note that the semiconductor memory device targeted here is DIET (DIET).
electrically encapsulated
dynamic random access memory with trench capacitor structure called capacitor cell
m access memory: DRAM) (for a DIET capacitor cell, e.g. r
lEEE International Elec
tron Devices Meeting D
(See EC, 1986 Lecture Proceedings, Lecture No. 6.3J).

In the figure, l is a p-type silicon semiconductor substrate, 2 is an n-type impurity diffusion region, 3 is a field insulating film made of silicon dioxide (SiOz), and 4 is a phosphosilicate glass (phosphorus silicate glass).
5 is an electrode/wiring (lower layer electrode/wiring) which is a bit line made of aluminum (A1 alloy), 7 is PS
A cover film consisting of G, 8 is a trench capacitor part,
9 is a dielectric film made of 5i02 in the trench capacitor part, 10 is an electrode film made of polycrystalline silicon in the trench capacitor part, 11 is a capacitor lead wiring made of polycrystalline silicon, and 12 is made of polycrystalline silicon. 13 is the edge of the field insulating film 3, 14 is the edge of the capacitor lead wiring 11 made of polycrystalline silicon, 15 is the electrode contact window for connecting the n-type impurity diffusion region 2 and the bit line 5, and 16 is the edge of the field insulating film 3. The edges of trench capacitor portions 8 are shown respectively.

Figures 12 and 13 clearly show the characteristics of the electrodes and wiring in this conventional semiconductor memory device.
As can be seen by focusing on, for example, the bit line 5 in these figures, it will be understood that as semiconductor elements become smaller, the pinch of the wiring must be reduced.

[Problem to be solved by the invention]

Usually, /1 alloy is used for wiring in semiconductor devices.

However, if the Aβ alloy wiring is made thinner, disconnection due to stress migration is more likely to occur, which impairs reliability. Particularly, as the width of the wiring becomes finer than 1 [μm], the frequency of wire breakage increases, which becomes a factor that hinders high integration.

Furthermore, when the pinch is small (as the pinch occurs), the parasitic capacitance due to the insulating film between the wirings becomes a non-negligible value, which causes the problem that the operation of the semiconductor memory device becomes slow.

The present invention provides a semiconductor device that achieves problems such as high integration, high speed, and improved reliability of electrodes and wiring by simple means.

[Means to solve the problem]

1 to 4 are for explaining the present invention in detail. FIG. 1 is a plan view of main parts of a semiconductor memory device, and FIG.
Part 3 cutaway side view along the line XI-XI seen in the figure.
The figure is the same <vAX2-X2 cutaway side view of the main part, 4th
The drawings also each represent a cutaway side view of the main part along the line Yl-Yl, and the same symbols as those used in FIGS. 11 to 14 represent the same parts or have the same meanings. Note that here as well, the semiconductor memory device in question is DI.
Although it is a DRAM with ET capacitor cells,
Since the present invention deals with the electrode/wiring structure, the structure in the bulk is not limited to the illustrated example. Also,
Since the DRAM is taken up, the electrodes and wiring are explained as bit lines, but the invention is not limited to this.
In short, it can be applied to all electrodes and wirings that need to be formed repeatedly.

Now, here, the parts shown in FIG. 11 and not shown in FIG. 14 will be explained.

In FIGS. 1 to 4, reference numeral 6 indicates an electrode/wiring (upper layer electrode/wiring !vA) which is a bit line made of a /1 alloy.

As is clear from the figure, the electrode/wiring 5, which is a bit line, is formed in the lower layer, and the electrode/wiring 6, which is a bit line, is formed in the upper layer. They are arranged so closely that some of them overlap. Originally, the bit and node wires are formed on the same layer with a predetermined spacing between them, and have exactly the same function, so in comparison, in the case of the present invention, as electrodes and wiring (bit vA). The function remains the same, but the pitch can be significantly reduced, making it possible to widen the width of the electrodes/wirings themselves, widening the spacing between electrodes/wirings belonging to the same layer, or reducing the occupied area. is possible.

According to the present invention, the pitch of the electrodes/wirings can be reduced by determining how small the electrode/wiring pitch is when the electrode contact window for the upper layer electrodes/wirings passes between the lower layer electrodes/wirings and reaches the contact point. The decision depends on whether or not a configuration can be adopted. In addition, since the electrode contact window for the upper layer electrode/wiring is deep to the contact point, for example to the semiconductor substrate, selective chemical vapor deposition (chemical vapor deposition) is used to fill the inside with a conductive material.
Tungsten (W) is grown using a CVD method or an A1 alloy is formed using a high temperature bias sputtering method to prevent the conductive material from being cut within the electrode contact window.

For this reason, in the semiconductor device according to the present invention, the semiconductor device is formed on a semiconductor substrate (for example, p-type silicon semiconductor substrate 1) and is repeatedly formed at intervals that allow the electrode contact windows to pass through. Arranged homogeneous electrodes
A wire (for example, an electrode/wiring 5) is formed on the electrode/wiring via an interlayer insulation M (for example, an interlayer insulating film 4), and is formed so densely that its longitudinal edges overlap the longitudinal edges of the electrode/wiring. It is provided with electrodes and wirings of the same type as the electrodes and wirings (for example, electrodes and wirings 6) arranged repeatedly.

[Effect]

By taking the above measures, if the density of the underlying semiconductor element is the same, it is possible to make the electrodes/wirings wider or the spacing between the electrodes/wirings wider compared to conventional ones. If it is possible to increase the reliability and operation speed of semiconductor devices, and if it is possible to increase the density of semiconductor elements, it is possible to easily achieve high integration without having to forcefully pack in electrodes and wiring. be able to.

〔Example〕

5(A) to (F) and FIG. 6(A) to (F) represent cutaway side views of essential parts of a semiconductor device at important process points for explaining one embodiment of the present invention. , will be explained with reference to these figures. It should be noted that Figure 5 is for explaining the contact between the lower layer electrode and the semiconductor substrate, and is similar to Figure 2, and Figure 6 is for explaining the contact between the upper layer electrode and the semiconductor substrate. This is a diagram similar to FIG. 3.

In this manufacturing process, as described above, a semiconductor memory device is targeted, and until the active region is formed, a normal bipolar or MIS (metal insulator 5
6H1iconductor) The manufacturing process is the same as that of a semiconductor memory device. The diagram shows transistors, capacitors,
Formation of active and passive elements such as resistors, or static random access memory (static
rand.

It is assumed that the process of forming a base such as intra-cell connections and word lines in the memory (maccess msmory: SRAM) has been completed. In the figure, the p-type silicon semi-dedicated substrate 21 is
A type impurity diffusion region 22, a field insulating film 23 made of S i 02, and an interlayer insulating film 24 made of PSG are shown.

Next, as a subsequent step, the case of forming a bit line made of an Af gold alloy will be described.

See Figures 5(A) and 6(A) (11 Resist process and reactive ion etching (reac) in normal photolithography technology.
By applying a tive ion etching (RIE) method, the interlayer insulating film 24 with a thickness of 1 cm μm is selectively etched to form, for example, electrode contact windows 24A for bit lines in odd-numbered columns.

Refer to FIG. 5(B) and FIG. 6(B) (21WF6 and 5z-i are used as source gases, and only the surface of the silicon semiconductor substrate 21 exposed in the electrode contact window 24A has a thickness of 0. A buried conductive film 25 made of tungsten (W) having a thickness of about .8 [μm] is selectively grown.

This selective growth results in WF s: 3 (SCCM),
S i H4: At a flow rate of 3 (SCCM), the pressure of WF6 and SiH4 was 3X10-2 (Torr), hydrogen (H2) was used as the carrier gas, and the temperature was 22
Execute with 0['lll:).

(3) By applying a sputtering method, a /1 alloy film having a thickness of about 1 [μm] is formed.

(4) Resist process in normal photolithography technology and etching of BCI 3 +Cβ2
By applying the RIE method using gas, the AN alloy film is patterned to form odd-numbered columns of bit lines (lower layer electrodes/wirings) 26. It goes without saying that this bit line 26 is in contact with the silicon semiconductor substrate 21 via the buried conductive film 25.

See Figures 5(C) and 6(C) (by applying the 51CVD method, the thickness is 1 [μm
] An interlayer insulating film 27 made of PSG is deposited.

(6) By applying the spin coating method, a solution containing silicon oxide dissolved in a solvent is applied, heated to diffuse the solvent, and a spin-on glass is applied to the recess of the interlayer insulating film 27. (spin.

n glass: SOG, e.g. 0CD manufactured by Tokyo Ohka)
A film 28 is formed.

By applying +7+CVD method, thickness 1 [μm
] An interlayer insulating film 29 made of PSG is deposited.

(8) By applying a spin coating method, a photoresist film 30 with a thickness of about 1 [μm] is formed.

By doing so, the wafer surface is flattened.

See Figures 5 (D) and 6 (D). (9) Apply the dry etching method and set conditions such that the etching rates of photoresist and PSG are the same, and etching the entire surface. The process is stopped when the top surface of the interlayer insulating film 27 is exposed, and the remaining photoresist film 30 is peeled off and removed.

Refer to FIG. 5(E) and FIG. 6(E) 00) By applying normal photolithography technology, even-numbered bits are formed between the bit lines 26 so as to reach the surface of the silicon semiconductor substrate 21 from the surface. Form an electrode contact window 24B associated with the line.

This requires selective etching of the interlayer insulating film 29, the SOG film 28, the interlayer insulating film 27, and the interlayer insulating film 24, and the total thickness thereof is about 3 [μm].

Refer to FIG. 5(F) and FIG. 6(F). 0υ WF6 and SiH4 are used as source gases, and a thickness of 2.8 [ μm]
A buried conductive film 31 consisting of the following is selectively grown.

The conditions for performing this selective growth are the same as those for forming the buried conductive film 25.

By applying the sub-sputtering method, the thickness can be reduced to 1
An Aβ alloy film having a size of approximately [μm] is formed.

α Yu Resist process and BC/! in normal photolithography technology! By applying the RIE method using 3 + (1! 2) as an etching gas, the A1 alloy film is patterned to form bit lines (
Upper layer electrodes/wirings) 32 are formed. This bit line 32
is the silicon semiconductor substrate 21 via the buried conductive film 31.
Needless to say, we are in contact with.

By applying the 04JCVD method, a thickness of 1 [μm
] A cover film 33 made of PSG of about 100% is deposited, and by applying a normal photolithography technique, the cover film 33 is selectively etched to form a bonding pad portion to complete the process.

In the manufacturing process, the buried conductive films 25 and 31 made of W selectively formed in the electrode contact windows 24A and 24B are obtained by reducing WF6 with SiH4. Selected W deposition method, Ajl! High temperature bias sputtering deposition of alloys and other known means may be used as appropriate. In addition, we used two layers of electrodes and wiring that extend in parallel.
Of course, based on this, three or more layers of the same structure may be stacked.

Figures 7 (A) to (F) and Figures 8 (A) to (F)
1 shows a cutaway side view of a main part of a semiconductor device at a key point in the process for explaining another embodiment of the present invention, and the following description will be made with reference to these figures. It should be noted that FIG. 7 is for explaining the contact between the lower layer electrode and the semiconductor substrate.
FIG. 8 is a diagram similar to FIG. 3, and is for explaining the contact between the upper layer electrode and the semiconductor substrate, and is similar to FIG. 5 and FIG. The same symbols as those used indicate the same parts or have the same meaning.

This manufacturing process has much in common with the manufacturing process described with reference to FIGS. 5 and 6, and therefore important points will be described in detail.

Refer to FIGS. 7(A) and 8(A). (1) The interlayer insulating film 24 is selectively etched by applying the resist process and RIE method in normal photolithography technology. , electrode contact windows 24A for bit lines in odd-numbered columns and electrode contact windows 24B for bit lines in even-numbered columns are simultaneously formed.

Refer to FIG. 7(B) and FIG. 8(B) CV using f21WF6 and SiH4 as source gas
By applying method D, buried conductive films 25A and 25B made of W are selectively grown only on the surface of silicon semiconductor substrate 21 exposed within electrode contact windows 24A and 24B.

(3) A sputtering method is applied to deposit an A1 alloy film, and then a conductivity improving film 34 made of W and having a thickness of about 1000 cm is deposited.

(4) By applying the resist process in normal photolithography technology, the RIB method using SF6 as an etching gas, and the same RIE method using BC53+C12 as an etching gas, the conductivity improving film can be formed. 34 and A1 alloy films are patterned to form odd rows of bits &'! Conductive film 26' that forms (lower layer electrode/wiring) 26 and contacts buried conductive film 25B corresponding to even-numbered column bit lines (upper layer electrode/wiring)
form.

Refer to FIGS. 7(C) and 8(C) (51) By applying the CVD method, an interlayer insulating film 27 made of PSG is deposited.

(6) Form the SOC film 28 in the recess of the interlayer insulating film 27 by applying the spin coating method.

An interlayer insulating film 29 made of PSG is deposited by applying the +7JCVD method.

(8) Form a photoresist film 30 by applying a spin coating method.

See Figures 7 (D) and 8 (D). (9) Apply the dry etching method and set conditions such that the etching rates of photoresist and PSG are the same, and etching the entire surface. The process is stopped when the top surface of the interlayer insulating film 27 is exposed, and the remaining photoresist film 30 is peeled off and removed.

Refer to FIG. 7(E) and FIG. 8(E) α1) Electrode contacts related to even-numbered bit lines are formed so as to reach the conductive film 26' from the surface by applying ordinary photolithography technology. A window 24B is formed.

This requires selective etching of the interlayer insulating film 29, SOG film 28, and interlayer insulating film 27, and the total thickness thereof is about 1.5 [μm].

CVD using QDWF6 and SiH4 as source gas, see FIG. 7(F) and FIG. 8(F)
By applying the method, a thickness of 1.3 [μm] is formed only on the conductive film 26' exposed in the electrode contact window 24B.
] The buried conductive film 31 made of W is selectively grown. It goes without saying that the buried conductive film 31 contacts the conductivity improving film 34 on the surface of the conductive film 26'.

ano Applying the sputtering method, A7! Forms an alloy film.

α Gloss Resist process in normal photolithography technology and etching BCI 3 C12
By applying the RIE method using gas, the A4 alloy film is patterned to form even-numbered columns of bit lines (upper layer electrodes/wirings) 32.

04) Depositing a cover film 33 made of PsG by applying the CVD method, and selectively etching the cover film 33 by applying a normal photolithography technique to form a bonding pad portion. and complete it.

In this manufacturing process, as compared with the manufacturing process described with reference to FIGS. 5 and 6, the electrode contact windows 24B associated with the even-numbered bit lines 32 are shallower, so the buried conductive film 31 can be easily formed.

Figures 9(A) to (F) and Figures 10(A) to (F)
) represents a cutaway side view of a main part of a semiconductor device at a key point in the process for explaining still another embodiment of the present invention, and the following description will be made with reference to these figures. Note that FIG. 9 is a diagram for explaining the contact between the lower layer electrode and the semiconductor substrate, and is similar to FIG. 2, and FIG. 10 is for explaining the contact between the upper layer electrode and the semiconductor substrate. This figure is similar to FIG. 3, and the same symbols as those used in FIGS. 5 to 8 indicate the same parts or have the same meanings.

This manufacturing process has much in common with the manufacturing process described with reference to FIGS. 5 to 8, and therefore important points will be described in detail.

Refer to FIGS. 9(A) and 10(A). (1) By applying the resist process and RIE method in photolithography technology, the interlayer insulating film 24 is selectively etched, The electrode contact window 24A for the second bit line and the electrode contact window 24B for the even-numbered bit line are formed at the same time.

See FIGS. 9(B) and 10(B) (21By applying the CVD method, the buried conductive film 25A and 25B is selectively grown.

(3) By applying the sputtering method, A
1 alloy film is deposited.

(4) By applying the resist process and RIE method in normal photolithography technology, A4
The alloy film is patterned to form odd-numbered columns of bit lines (lower layer electrodes/wirings) 26.

Referring to FIGS. 9(C) and 10(C), an interlayer insulating film 27 made of PSG is deposited by applying the f51CVD method.

(6) SOG film 28 is formed in the recess of interlayer insulating film 27 by applying a spin coating method.

(By applying the 71CVD method, an interlayer insulating film 29 made of PSG is deposited.

(8) Form a photoresist film 30 by applying a spin coating method.

Refer to FIGS. 9(D) and 10(D). (9) Dry etching is applied to the entire surface, stopping when the top surface of the interlayer insulating film 27 is exposed, and the remaining photo is etched. - Peel and remove the resist film 30.

Refer to FIGS. 9(E) and 10(E) 00) By applying normal photolithography technology, electrode contacts related to even-numbered column bit lines are formed so as to reach the buried conductive film 25B from the surface. Window 24B
form.

This requires selective etching of the interlayer insulating film 29, SOG film 28, and interlayer insulating film 27, and the total thickness thereof is about 2.2 [μm].

Refer to FIG. 9(F) and FIG. 10(F) 00 By applying the CVD method, the buried conductive film 2.5B exposed in the electrode contact window 24B
A buried conductive film 31 made of W and having a thickness of about 2.0 [μm] is selectively grown thereon.

A Qδ sputtering method is applied to form a /1 alloy film.

031 By applying the resist process and RIE method in normal photolithography technology,
The Af alloy film is patterned to form even-numbered columns of bit lines (upper layer electrodes/wirings) 32.

(By applying the +41CVD method, a cover film 33 made of PSG is deposited, and by applying a normal photolithography technique, the cover film 33 is selectively etched to form a bonding pad portion. and complete it.

Although this manufacturing process is different from the manufacturing process described with reference to FIGS. 7 and 8, it is possible to form shallow electrode contact windows 24B associated with bit lines 32 in even-numbered columns.

〔Effect of the invention〕

In the semiconductor device according to the present invention, the same type of electrodes/wirings are arranged repeatedly at intervals that allow the electrode contact windows to penetrate therebetween, and the electrodes/wirings are arranged on the electrodes/wirings with an interlayer insulating film interposed therebetween. The same type of electrodes and wirings as the electrodes and wirings are formed and repeatedly arranged densely to such an extent that the edges in the horizontal direction overlap the edges in the horizontal direction of the electrodes and wirings.

By adopting the above configuration, assuming the density of the underlying semiconductor element is the same, it is possible to make the electrodes/wirings wider or to increase the spacing between the electrodes/wirings compared to conventional ones. In addition, if there is enough room to increase the density of various areas in the semiconductor device, electrodes and wiring can be packed together (but it is easy to achieve high integration). can be converted into

[Brief explanation of the drawing]

1 is a plan view of the main part of a semiconductor device for explaining the present invention in detail, FIG. 2 is a side view of the main part cut away along the line X1-Xi seen in FIG. 1, and FIG. The line X2-X seen in
2, FIG. 4 is a side view of the main part cut away along line Y1-Y1 seen in FIG. 1, FIGS. 5(A) to (F), and FIG. 6(A). 7(A) to 8(F) are cross-sectional side views of essential parts of a semiconductor device at key process points for explaining embodiments of the present invention, FIGS. 7(A) to 8(F), and FIGS. 8(A) to 8(F). (F) is a cutaway side view of the main part of a semiconductor device at key points in the process for explaining another embodiment of the present invention;
Figures 9(A) to (F) and Figures 10(A) to (F)
) is a cutaway side view of the main part of a semiconductor device at a key point in the process for explaining still another embodiment of the present invention, and FIG. 11 is a plan view of the main part of the semiconductor device for explaining a conventional example. , 12th
The figure is a cutaway side view of the main part along the line X1-X1 seen in Figure 11, and Figure 13 is the line X2-X2 seen in Figure 11.
FIG. 14 shows a cutaway side view of the main part taken along the line Yl--Yl shown in FIG. 11, respectively. In the figure, 1 is a p-type silicon semiconductor substrate, 2 is an n-type impurity diffusion region, 3 is an SiO2 field insulating film, 4 is a PSG interlayer insulating film, and 5 is an A6 alloy bit line electrode/wiring ( 6 is the A4 alloy bit line electrode/wiring (upper layer electrode/wiring), 7 is PSG
8 is a trench capacitor part, 9 is a dielectric film made of 5i02 in the trench capacitor part, 10 is an electrode film made of polycrystalline silicon in the trench capacitor part, 11 is made of polycrystalline silicon. 12 is a word line made of polycrystalline silicon; 13 is an edge of the field insulating film 3; 14 is a word line made of polycrystalline silicon;
is a capacitor lead-out wiring 11 made of polycrystalline silicon.
, 15 indicates an electrode contact window for connecting the n-type impurity diffusion region 2 and the bit line 5, and 16 indicates the edge of the trench capacitor portion 8, respectively. l A cut-away side view of the main part taken along the line XI-XI in Fig. 1 Fig. 2 A cut-away side view of the main part taken along the line X2-X2 in Fig. 1 Fig. 3 Fig. 12 Fig. 13

Claims (1)

[Scope of Claims] Same type of electrodes/wirings formed on a semiconductor substrate and repeatedly arranged at intervals that allow electrode contact windows to pass through, and an interlayer insulating film on the electrodes/wirings. 1. A semiconductor device comprising electrodes and interconnects of the same type as the electrodes and interconnects, which are formed through the electrodes and interconnects and repeatedly arranged so densely that their longitudinal edges overlap the longitudinal edges of the electrodes and interconnects.