JPH0426156A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0426156A JPH0426156A JP2130252A JP13025290A JPH0426156A JP H0426156 A JPH0426156 A JP H0426156A JP 2130252 A JP2130252 A JP 2130252A JP 13025290 A JP13025290 A JP 13025290A JP H0426156 A JPH0426156 A JP H0426156A
- Authority
- JP
- Japan
- Prior art keywords
- polysilicon
- charge storage
- film
- contact hole
- capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 74
- 229920005591 polysilicon Polymers 0.000 claims abstract description 74
- 239000003990 capacitor Substances 0.000 claims abstract description 36
- 238000000034 method Methods 0.000 claims abstract description 18
- 238000005530 etching Methods 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000003860 storage Methods 0.000 claims description 47
- 238000000059 patterning Methods 0.000 abstract description 7
- 238000009413 insulation Methods 0.000 abstract description 5
- 238000009825 accumulation Methods 0.000 abstract 6
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
この発明は半導体装置の製造方法に係り、詳しくは、半
導体ダイナミック・ランダム・アクセス・メモリ （Ｄ
Ｒ，Ａ Ｍ ）におけるキャパシタの製造方法に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a semiconductor device, and specifically relates to a semiconductor dynamic random access memory (D
The present invention relates to a method for manufacturing a capacitor in R, A M ).
（従来の技術）
ＤＲＡＭの高密度化を図るために、単位セル面積当りの
情報蓄積用キャパシタ容量を増加させる試みが従来、多
々行われている。例えば文献「イクステンデット・アブ
ストラクッ・オン・ザ・２０ス・コンファレンス・オン
・ソリッド・ステイク・デバイシス・アンド・マテリア
ルズ、トーキ！ｌ −（Ｅｘｔｅｎｄｅｄ Ａｂｓｔｒ
ａｃｔｓ ｏｆ ｔｈｅ ２０ｔｈ Ｃｏｎｆｅｒｅｎ
ｃｅ ｏｎ ５ｏｌｉｄ ５ｔａｔｅ Ｄｅｖｉｃｅｓ
ａｎｄ ＭａｔｅｒｉａｌｓＴｏｋｙｏ）、 １９８
８． ＰＰ、５８１ ５８４Ｊに開示され、第４図に示
すように、キャパシタの電荷蓄積電極を、第１と第２の
ポリシリコン１，２を用いて２層に積み重ねて形成して
、電荷蓄積電極の表面積を増大させることにより、キャ
パシタ容量の増大を図っている。(Prior Art) In order to increase the density of DRAMs, many attempts have been made to increase the capacity of an information storage capacitor per unit cell area. For example, the document ``Extended Abstracts on the 20th Conference on Solid Stake Devices and Materials, Talk!
acts of the 20th Conference
ce on 5solid 5tate Devices
and Materials Tokyo), 198
8. PP, 581 584J, and as shown in FIG. 4, the charge storage electrode of the capacitor is formed by stacking the first and second polysilicon layers 1 and 2 in two layers. By increasing the surface area, the capacitor capacity is increased.
（発明が解決しようとする課題）
しかるに、上記の方法では、ある程度のキャパシタ容量
の増大は期待できるものの、デバイスの縮小化が進み、
平面的に縮小化されると、やはり容量が充分なものとな
らず、技術的に満足できるものではなかった。また、上
記電荷蓄積電極は実際は複数個隣接して形成されるわけ
であるが、デバイスの縮小化が進んで、隣接電荷蓄積電
極間（隣接キャパシタ間）の距離が小さくなった場合に
は、ホトリソグラフィの時点で、隣接ｉｔ電荷蓄積電極
間段差部分においてホトレジストのブリフジが発生する
ので、ポリシリコンの第４図のような完全なパターニン
グが困難となり、ポリシリコン残渣で電荷蓄積電極間が
ショートする問題があった。(Problem to be Solved by the Invention) However, although the above method can be expected to increase the capacitor capacity to a certain extent, the device size continues to decrease,
When it is reduced in size, the capacity is still not sufficient and it is not technically satisfactory. Furthermore, although multiple charge storage electrodes are actually formed adjacent to each other, as devices become smaller and the distance between adjacent charge storage electrodes (between adjacent capacitors) becomes smaller, At the time of lithography, photoresist bridging occurs at the stepped portion between adjacent IT charge storage electrodes, making it difficult to completely pattern polysilicon as shown in Figure 4, and causing a short circuit between the charge storage electrodes due to polysilicon residue. was there.
この電極間ショートは、文献ｒｌＥＤＭ８９Ｐ３１〜Ｐ
３３」に開示され、第５図に示すように、すぐ横に隣接
する電荷蓄積電極１１ｂを別の層で形成すれば、事実上
電極間間隔（同一平面上の電極間間隔）が拡大するので
、解消することができる。This short between the electrodes is explained in the literature rlEDM89P31~P.
33, and as shown in FIG. 5, if the immediately adjacent charge storage electrode 11b is formed in a separate layer, the inter-electrode spacing (the spacing between electrodes on the same plane) can be expanded. , can be resolved.
しかるに、上記文献に開示される方法では、前記第５図
に示すように、電荷蓄積電極１１ａ１１ｂを基板１２の
トランジスタに隣接する部分１３を比較的大きなコンタ
クトホール（電荷蓄積電極の厚さの２倍を越える径のコ
ンタク（・ホール）で形成しているので、この接続部に
おいて電荷蓄積電極１１ａ、１１．ｂの表面に凹部１４
いわゆる゛巣゛が発生し、電荷蓄積電極１１ａ、ｌｌｂ
の表面にキャパシタ絶縁膜を形成した際に、その凹部１
４部分でキャパシタ絶縁膜の膜厚均一性が１員われるか
ら、信顛性の高いキャパシタを製造することができなか
った。また、平面部分だけで電荷蓄積電極面積を確保し
ているので、デバイスの縮小化に伴い、第４図の構造以
上に容量不足が懸念される。However, in the method disclosed in the above-mentioned document, as shown in FIG. Since the contacts (holes) have a diameter exceeding
A so-called "nest" occurs, and the charge storage electrodes 11a, llb
When a capacitor insulating film is formed on the surface of the recess 1
Since the film thickness uniformity of the capacitor insulating film is affected by one factor in the four parts, a highly reliable capacitor cannot be manufactured. Further, since the area of the charge storage electrode is secured only in the planar portion, there is a concern that the capacitance will be insufficient as the device becomes smaller than the structure shown in FIG. 4.
この発明は上記の点に鑑みなされたもので、デバイスの
縮小化が進んでもキャパシタ容量を大きくとることがで
き、かつ電荷蓄積電極の表面に均一にキャパシタ絶縁膜
を形成できて信頼性の高いキャパシタを製造することが
でき、さらにはデバイスの縮小化に伴う電極間ショート
も防止でき、製造歩留りを向上させることができる半導
体装置の製造方法を提供することを目的とする。This invention was made in view of the above points, and it is a highly reliable capacitor that can have a large capacitance even as devices become smaller, and can form a capacitor insulating film uniformly on the surface of the charge storage electrode. It is an object of the present invention to provide a method for manufacturing a semiconductor device, which can also prevent short-circuits between electrodes due to device miniaturization, and can improve manufacturing yield.
（！！題を解決するための手段）
この発明では、半導体基板上に絶縁膜を形成する工程、
半導体基板上絶縁膜に微細なコンタクトホールを開ける
工程、そのコンタクトホールと絶縁膜表面にポリシリコ
ンを形成し、絶縁膜表面のポリシリコンをパターニング
する工程、得られたポリシリコンパターン上を含む前記
絶縁膜表面に、ポリシリコン七エツチング選択性を有す
る膜を形成し、この膜に前記ポリシリコンパターン上で
複数の孔を開ける工程、その孔をポリシリコンで埋め込
む工程、前記ポリシリコンとエツチング選択性を有する
膜を除去する工程をキャパシタのｉｉ荷Ｍ積電極形成工
程として有し、この工程を２回繰り返し、１回目で隣接
する？！数の電荷蓄積電極のうち１つ置きの複数の電荷
蓄積電極を形成し、２回目で残りの複数の電荷蓄積電極
を前記１回目による１を荷蓄積電極の上方に位置を移し
て形成する。(!!Means for solving the problem) In the present invention, a step of forming an insulating film on a semiconductor substrate,
A step of forming a fine contact hole in an insulating film on a semiconductor substrate, a step of forming polysilicon on the contact hole and the surface of the insulating film, and a step of patterning the polysilicon on the surface of the insulating film. Forming a film having polysilicon etching selectivity on the film surface, forming a plurality of holes in this film on the polysilicon pattern, filling the holes with polysilicon, and etching selectivity with the polysilicon. The step of removing the film containing the capacitor is the step of forming the capacitor's electrodes, and this step is repeated twice, and the first step is to remove the adjacent film. ! A plurality of charge storage electrodes are formed every other charge storage electrode among the number of charge storage electrodes, and in the second time, the remaining charge storage electrodes are formed by moving the position 1 from the first time above the charge storage electrodes.
（作 用）
上記この発明においては、絶縁股上に形成されたポリシ
リコンパターンと、ポリシリコンとエツチング選択性を
有する膜の孔内を埋めたポリノリコンとにより、例えば
第１図ｆｇｌに示すように平板上に複数のポリシリコン
の柱を有する形状に電荷蓄積電極が形成される。この形
状によれば、垂直方向を電荷蓄積電極の表面積増大に積
極的に利用しているので、デバイスが平面的に縮小され
ても電荷蓄積電極の表面積を大きくとることができ、大
きなキャパシタ容量を得ることができる。また、このｔ
荷蓄積電極は、絶縁膜に開けたコンタクトホール部で半
導体基板（より詳細には半導体基板に形成されたトラン
スファゲートとしてのＭＯ５型トランジスタ）と接続さ
れるが、前記コンタクトホールを微細なコンタクトホー
ル（具体的には′ｖＪ、荷蓄積電極を形成する前記ポリ
シリコンパターンの厚さの２倍以下の径のコンタクトホ
ール）とすることにより、前記ポリシリコンパターンお
よびコンタクトホール内を埋めるポリシリコンを形成す
るためのポリシリコン堆積時に、該ポリシリコンひいて
は、それをパターニングした前記ポリシリコンパターン
にコンタクトホール部で巣（凹部）が発生することを防
止できる。したがって、電荷蓄積電極表面のキャパシタ
絶縁膜は全体にわたり均一な膜厚となる。また、複数の
隣接する電荷蓄積電極は例えば第３図（この図ではポリ
シリコンの柱は省略して描いである）に示すように交互
に上下に位置を変えて形成されることになり、したがっ
て、同一平面における電極間隔は、すべてを同一平面に
並べる場合に比べて拡大できる。(Function) In the present invention, the polysilicon pattern formed on the insulating crotch and the polysilicon filled in the pores of the film having etching selectivity with polysilicon are used to form a flat plate as shown in FIG. A charge storage electrode is formed in the shape of having a plurality of polysilicon pillars thereon. According to this shape, the vertical direction is actively used to increase the surface area of the charge storage electrode, so even if the device is reduced in plan, the surface area of the charge storage electrode can be increased, and a large capacitance can be achieved. Obtainable. Also, this t
The charge storage electrode is connected to a semiconductor substrate (more specifically, an MO5 type transistor as a transfer gate formed in a semiconductor substrate) through a contact hole formed in an insulating film. Specifically, by forming the contact hole with a diameter less than twice the thickness of the polysilicon pattern forming the charge storage electrode, polysilicon is formed to fill the inside of the polysilicon pattern and the contact hole. During the deposition of polysilicon for the purpose of the present invention, it is possible to prevent cavities (concave portions) from occurring in the contact hole portions of the polysilicon and, by extension, of the polysilicon pattern formed by patterning it. Therefore, the capacitor insulating film on the surface of the charge storage electrode has a uniform thickness over the entire surface. In addition, a plurality of adjacent charge storage electrodes are formed by alternating their positions vertically, as shown in FIG. 3 (in this figure, the polysilicon pillars are omitted). , the electrode spacing on the same plane can be increased compared to when all the electrodes are arranged on the same plane.
よって、電極パターニング（ポリシリコンパターニング
）が容易かつ確実となり、ポリシリコン残渣で電極間が
ショートすることがなくなる。Therefore, electrode patterning (polysilicon patterning) becomes easy and reliable, and short circuits between the electrodes due to polysilicon residues are prevented.
（実施例） 以下この発明の一実施例を第１図を参照して説明する。(Example) An embodiment of the present invention will be described below with reference to FIG.
一実施例では、まず第１図（８）に示すように、Ｐ型シ
リコン基板２１にイオン注入と選択酸化法によりチャネ
ルストップ層２２とフィールド酸化膜２３を形成する。In one embodiment, first, as shown in FIG. 1(8), a channel stop layer 22 and a field oxide film 23 are formed on a P-type silicon substrate 21 by ion implantation and selective oxidation.
次に、アクティブ頭載の基Ｆｉ２’１表面に第１図ｔｂ
＋に示すようにゲート酸化膜２４とゲート電極２５を形
成し、さらに第１図（ｃｌに示すように一対のＮ”拡散
Ｎ２６ ａ 、 ２６ ｂをソース・ドレインとして
基板２１内に形成することにより、トランスファゲート
としてのＭＯ３型トランジスタを完成させる。Next, on the surface of the active head-mounted group Fi2'1,
By forming a gate oxide film 24 and a gate electrode 25 as shown in FIG. , completes an MO3 type transistor as a transfer gate.
次に、常圧ＣＶＤあるいはＴＥ０１ （テトラエトキシ
シラン）−ＣＶＤ法による５００ｎ−厚の酸化膜の形成
と、全面エッチバックによる表面平坦化により、第１図
（ｃ）に示すように仕上り膜厚３００ｎｍ程度の表面の
平坦な酸化膜２７を絶縁膜として基板２１上の全面に形
成する。そして、その酸化膜２７に通常のホトリソ・工
・ノチング法で前記一方の拡散！１５２６ａ上でコンタ
クトホール２８を間ける。ここで、このコンタクトホー
ル２８は、次にキャパシタの電荷蓄積電極を形成するた
めに前記酸化膜２７上に形成されるポリシリコンの膜１
’ｆ（２００ｎ＠）の２倍以下の径の微細なコンタクト
ホールとする。Next, a 500n-thick oxide film was formed by normal pressure CVD or TE01 (tetraethoxysilane)-CVD, and the surface was flattened by etching back the entire surface, resulting in a final film thickness of 300nm as shown in Figure 1(c). An oxide film 27 having a relatively flat surface is formed as an insulating film over the entire surface of the substrate 21. Then, the above-mentioned one is diffused into the oxide film 27 using the usual photolithography, etching, and notching methods. A contact hole 28 is formed above 1526a. Here, this contact hole 28 is connected to a polysilicon film 1 which is then formed on the oxide film 27 to form a charge storage electrode of a capacitor.
A fine contact hole with a diameter less than twice f(200n@) is used.
次に、コンタクトホール２８と酸化膜２７の表面にポリ
シリコンを２００ｎｓ堆積させ、これに導電性をもたせ
るためリンを５Ｘ１０”〜１×ＸＯ’。Next, polysilicon is deposited on the surface of the contact hole 28 and the oxide film 27 for 200 ns, and 5×10'' to 1×XO' of phosphorus is added to make it conductive.
値１程度の濃度でドープした後、酸化膜２７表面のポリ
シリコンを通常のホトリソ・エツチング法でパターニン
グすることにより、キャパシタの電荷蓄積電極の一部と
なる平板状のポリシリコンパターン２９を第１図ｆｄ）
に示すように形成する。この時、コンタクトホール２８
が上述のように微細であったため、堆積ポリシリコンひ
いては、それをパターニングしたポリシリコンパターン
２９の」−面には巣（凹部）が発生しない。また、この
ポリシリコンパターン２９は、コンタクトホール２Ｂ内
に残ったポリシリコン２９ａによりＭＯ３型トランジス
タの一方の拡散層２６ａに接続される。After doping at a concentration of approximately 1, the polysilicon on the surface of the oxide film 27 is patterned using a normal photolithography/etching method to form a flat polysilicon pattern 29 that will become a part of the charge storage electrode of the capacitor. Figure fd)
Form as shown. At this time, contact hole 28
Since the polysilicon was so fine as described above, no cavities (concave portions) are generated on the negative surface of the deposited polysilicon and, by extension, of the polysilicon pattern 29 formed by patterning it. Further, this polysilicon pattern 29 is connected to one diffusion layer 26a of the MO3 type transistor by the polysilicon 29a remaining in the contact hole 2B.
次に、ポリシリコンと充分にエツチング選択性を有する
膜として酸化膜３０を、前記ポリシリコンパターン２９
上を含む酸化［２７の全表面に第１図１８）に示すよう
に５００〜８００ｎｍ厚に堆積させる。そして、この酸
化膜２７に、前記コンタクトホールより幾分大きい程度
の複数の孔３１＠通常のホトリソ・エツチング法で前記
ポリシリコンパターン２９上で開ける。Next, an oxide film 30 is formed on the polysilicon pattern 29 as a film having sufficient etching selectivity with respect to polysilicon.
Oxide is deposited to a thickness of 500 to 800 nm on the entire surface of [27] as shown in FIG. 18). Then, in this oxide film 27, a plurality of holes 31 somewhat larger than the contact holes are formed on the polysilicon pattern 29 by a normal photolithography/etching method.
その後、酸化１１１３０上の全面にポリシリコンを減圧
ＣＶＤ法で１１００Ｏｎｉ程度堆積させて、孔３Ｉをポ
リシリコンで完全に埋め込むとともに、そのポリシリコ
ンを前記ポリシリコンパターン２９と一体化させた後、
堆積ポリシリコンに不純物を導入して導電性をもたせ、
さらにその堆積ポリシリコンを酸化膜３０の表面まで全
面エソチバフクして前記孔３１内にのみ残すことにより
、孔３１内に第１図（ｆｌに示すようにポリシリコンの
柱３２を形成する。After that, about 1100 Oni of polysilicon is deposited on the entire surface of the oxide 11130 by low pressure CVD method, and the hole 3I is completely filled with polysilicon, and the polysilicon is integrated with the polysilicon pattern 29.
Introducing impurities into deposited polysilicon to make it conductive,
Further, the deposited polysilicon is etched all over the surface of the oxide film 30 and left only in the hole 31, thereby forming a polysilicon pillar 32 in the hole 31 as shown in FIG.
その後、酸化膜３０をフッ酸溶液あるいはプラズマエツ
チャーにより除去することにより、第１図（幻に示すよ
うにポリシリコンパターン２９ａおよびポリシリコンの
柱３２すなわちキャパシタの電荷蓄積電極３３を酸化膜
２７上に露出させる。Thereafter, by removing the oxide film 30 with a hydrofluoric acid solution or plasma etching, the polysilicon pattern 29a and the polysilicon pillars 32, that is, the charge storage electrodes 33 of the capacitor, are formed on the oxide film 27, as shown in FIG. to be exposed to.
その後、電荷蓄積電極３３の露出表面を含む全面に窒化
シリコン膜を減圧ＣＶＤ法により２０ｎｍ堆積させ、さ
らにその後９５０℃ウェット酸素雰囲気において熱酸化
を行って窒化シリコン膜の表面に２〜４ｎ■の酸化膜を
形成することにより、２ＩＩ造のキャパシタ絶縁Ｗ１．
３４を第１図ｆｈｌに示すように′ｒ！ｉ荷蓄積電極３
３の露出表面に形成する。さらに全面にポリシリコンを
減圧ＣＶＤ法で１００ｎ−堆積させ、これにリンを５Ｘ
１０！０ｃａ−’程度の濃度でドープした後、このポリ
シリコンをパターニングすることにより、前記１１？？
ｊ蓄積電極３３をキャパシタ絶縁膜３４を挾んで覆うキ
ャパシタのプレート電極３５を形成する。これによりキ
ャパシタが完成する。Thereafter, a silicon nitride film is deposited to a thickness of 20 nm on the entire surface including the exposed surface of the charge storage electrode 33 by low pressure CVD, and then thermal oxidation is performed in a wet oxygen atmosphere at 950°C to oxidize the surface of the silicon nitride film to a thickness of 2 to 4 nm. By forming a film, a 2II structure capacitor insulation W1.
34 as shown in Figure 1fhl'r! i charge storage electrode 3
Formed on the exposed surface of 3. Furthermore, 100n- polysilicon was deposited on the entire surface by low pressure CVD method, and phosphorus was added 5X to this.
After doping at a concentration of about 10!0ca-', this polysilicon is patterned to form the above-mentioned 11? ?
A capacitor plate electrode 35 is formed to cover the storage electrode 33 with the capacitor insulating film 34 interposed therebetween. This completes the capacitor.
このようなキャパシタ形成法で、第２図および第３図に
示す複数の隣接するキャパシタ（ただし、第２図および
第３図では電荷蓄積電極３３部分のみを、しかも第３図
ではポリシリコンの柱３２を省略して示しである）のう
ち、１つ置きの？１敗のキャパシタ３６ａを形成する。With this capacitor formation method, a plurality of adjacent capacitors shown in FIGS. 2 and 3 are formed (however, only the charge storage electrode 33 portion is formed in FIGS. 32 is omitted), every other one? A capacitor 36a with one loss is formed.
残りの複数のキャパシタ３６ｂは、第１図（ｃｌ〜第１
図ｆｈｌの工程を繰り返して、第１図（ｈｌの構造体上
に、キャパシタ３６ａより上方に位置を移して形成する
。この点を簡単に説明すると、まず第１図（ｈｌの構造
体上の全面に、第１図（１１に示すように酸化膜２７′
を形成する。その酸化膜２７′と酸化膜２７にコンタク
トホール２Ｂ′を開ける。その際、勿論、このコンタク
トホール２８′は、第２図に示すようにキャパシタ３６
ａが接続されたトランジスタと隣りのトランジスタの一
方の拡散層上で開ける。そのコンタクトホール２８′を
ポリシリコン２９ａ′で埋め、かつ酸化膜２７′上にポ
リシリコンパターン２９′を形成する。そのポリシリコ
ンパターン２９ａ′上に複数のポリシリコンの柱３２′
を形成する。その柱３２′とポリシリコンパターン２９
ａ′からなる電荷蓄積電極３３′の表面にキャパシタ絶
縁膜３４′を形成する・さらに、このキャパシタ絶縁ｉ
ｌｌ ３４’を挾んで電荷蓄積電極３３′を覆うキャパ
シタのプレート電極３５′を形成し、キャパシタ３６ｂ
を完成させる。The remaining capacitors 36b are arranged as shown in FIG.
By repeating the process shown in FIG. 1 (hl), the capacitor 36a is formed on the structure shown in FIG. An oxide film 27' is applied to the entire surface as shown in FIG.
form. A contact hole 2B' is opened in the oxide film 27' and the oxide film 27. At this time, of course, this contact hole 28' is connected to the capacitor 36 as shown in FIG.
A is opened on the diffusion layer of the connected transistor and one of the adjacent transistors. The contact hole 28' is filled with polysilicon 29a', and a polysilicon pattern 29' is formed on the oxide film 27'. A plurality of polysilicon pillars 32' are formed on the polysilicon pattern 29a'.
form. The pillar 32' and the polysilicon pattern 29
A capacitor insulating film 34' is formed on the surface of the charge storage electrode 33' consisting of a'.
A capacitor plate electrode 35' is formed to sandwich the ll 34' and cover the charge storage electrode 33', and the capacitor 36b is
complete.
その後は図示しないが全面に中間絶縁膜を形成し、ビッ
ト線接続用のコンタクトホールの開孔を行い、ビット線
を形成し、表面保護膜を形成し、この発明の一実施例に
よるスタック・キャパシタ構造のＤＲＡＭを完成させる
。After that, although not shown, an intermediate insulating film is formed on the entire surface, a contact hole for connecting a bit line is formed, a bit line is formed, a surface protection film is formed, and a stack capacitor according to an embodiment of the present invention is formed. Complete the DRAM structure.
（発明の効果）
以上詳細に説明したように、この発明の製造方法によれ
ば、平板上に複数のポリシリコンの柱を有する形状に電
荷蓄積電極が形成され、垂直方向を電荷蓄積電極の表面
積増大に積極的に利用する形状となるので、デバイスが
平面的に縮小されても電荷蓄積電極の表面積を大きくと
ることができ、大きなキャパシタ容量を得ることができ
る。(Effects of the Invention) As explained in detail above, according to the manufacturing method of the present invention, a charge storage electrode is formed in a shape having a plurality of polysilicon pillars on a flat plate, and the surface area of the charge storage electrode is Since the shape is actively utilized for increasing the charge storage electrode, the surface area of the charge storage electrode can be increased even if the device is reduced in plan, and a large capacitor capacity can be obtained.
よって、ソフトエラー耐性の大きい高信頼性のＤＲＡＭ
を製造できる。また、前記ｉｉｉ荷蓄積電極は、絶縁膜
に開けたコンタクトホール部で半導体基板（詳細にはト
ランジスタ）と接続されるが、前記コンタクトホールを
微細なコンタクトホールとすることにより、前記電荷蓄
積電極の平板部となるポリシリコンパターンおよびコン
タクトホールを埋めるポリシリコンを形成するためのポ
リシリコン堆積時に、該ポリシリコンひいては、それを
パターニングした前記ポリシリコンパターンにコンタク
トホール部で巣（凹部）が発生することを防止でき、し
たがって１ｉ電荷蓄積電極面のキャパシタ絶縁膜を全体
にわたり均一な膜厚とし得るから、この点からも高信頼
性のＤＲＡＭを製造できる。さらに複数の隣接する電荷
蓄積電極は交互に上下に位置を変えて形成されるから、
すべてを同一平面上に並べた場合に比較して同一平面上
で電極間間隔を広くとることができ、よって電極パター
ニングが容品かつ確実となり、ポリシリコン残渣で電極
間がショートすることを防止でき、製造歩留りを向上さ
せることができる。Therefore, highly reliable DRAM with high resistance to soft errors.
can be manufactured. Further, the charge storage electrode III is connected to a semiconductor substrate (specifically, a transistor) through a contact hole formed in an insulating film, and by making the contact hole a fine contact hole, the charge storage electrode When polysilicon is deposited to form a polysilicon pattern that will become a flat plate portion and polysilicon that fills a contact hole, cavities (concave portions) may occur in the contact hole portion of the polysilicon and, by extension, the polysilicon pattern that is patterned from the polysilicon. Therefore, the capacitor insulating film on the 1i charge storage electrode surface can be made to have a uniform thickness over the entire surface, and from this point as well, a highly reliable DRAM can be manufactured. Furthermore, since a plurality of adjacent charge storage electrodes are formed by alternating their positions vertically,
Compared to when all the electrodes are arranged on the same plane, the spacing between the electrodes can be made wider on the same plane, making electrode patterning simple and reliable, and preventing short circuits between the electrodes due to polysilicon residue. , manufacturing yield can be improved.
第１図はこの発明の半導体装置の製造方法の一実施例を
示す工程断面図、第２図および第３図はこの発明の一実
施例に係る電荷蓄積電極の配列状態を示す平面図および
斜視図、第４図および第５図は従来の電荷蓄積電極構造
を示す断面図および斜視図である。
２１・・・Ｐ型シリコン基板、２７．２７’・・・酸化
膜、２８．２８’・・・コンタクトホール、２９．２９
’・・・ポリシリコンパターン、２９ａ、２９ａ’・・
・ポリシリコン、３０・・・酸化膜、３１・・・孔、３
２．３２’・・・ポリシリコンの柱、３３．３３’・・
・電荷蓄積電極、３６ａ、３６ｂ・・・キャパシタ。
本発明の一実施例
第１
図
本発明の一実施例
第１
図
本発明の一実施例
第１
図
本発明（二係る配列（平面図）
第２図
本発明［係る配列（斜視図）
第３
図FIG. 1 is a process cross-sectional view showing an embodiment of the method for manufacturing a semiconductor device according to the present invention, and FIGS. 2 and 3 are plan views and perspective views showing the arrangement of charge storage electrodes according to an embodiment of the present invention. 4 and 5 are a cross-sectional view and a perspective view showing a conventional charge storage electrode structure. 21...P-type silicon substrate, 27.27'...Oxide film, 28.28'...Contact hole, 29.29
'...Polysilicon pattern, 29a, 29a'...
・Polysilicon, 30... Oxide film, 31... Hole, 3
2.32'...Polysilicon pillar, 33.33'...
- Charge storage electrodes, 36a, 36b...capacitors. Embodiment 1 of the present invention Fig. 1 Embodiment 1 of the present invention Fig. 1 Embodiment 1 of the present invention Fig. 2 The present invention (2 such arrangement (plan view)) Fig. 2 The present invention [2 such arrangement (perspective view) 3 diagram
Claims (1)
導体基板上絶縁膜に微細なコンタクトホールを開ける工
程、 （ｃ）そのコンタクトホールと絶縁膜表面にポリシリコ
ンを形成し、絶縁膜表面のポリシリコンをパターニング
する工程、 （ｄ）得られたポリシリコンパターン上を含む前記絶縁
膜表面に、ポリシリコンとエッチング選択性を有する膜
を形成し、この膜に前記ポリシリコンパターン上で複数
の孔を開ける工程、 （ｅ）その孔をポリシリコンで埋め込む工程、（ｆ）前
記ポリシリコンとエッチング選択性を有する膜を除去す
る工程 をキャパシタの電荷蓄積電極形成工程として有し、この
工程を２回繰り返し、１回目で隣接する複数の電荷蓄積
電極のうち１つ置きの複数の電荷蓄積電極を形成し、２
回目で残りの複数の電荷蓄積電極を前記１回目による電
荷蓄積電極の上方に位置を移して形成することを特徴と
する半導体装置の製造方法。[Claims] (a) A step of forming an insulating film on a semiconductor substrate, (b) A step of making a fine contact hole in an insulating film on a semiconductor substrate, (c) A process of forming a polysilicon film on the contact hole and the surface of the insulating film. (d) forming a film having etching selectivity with polysilicon on the surface of the insulating film including on the obtained polysilicon pattern; A step of forming a plurality of holes on a polysilicon pattern, (e) a step of filling the holes with polysilicon, and (f) a step of removing a film having etching selectivity with respect to the polysilicon is a step of forming a charge storage electrode of a capacitor. This process is repeated twice, forming a plurality of charge storage electrodes every other one among the plurality of adjacent charge storage electrodes in the first time, and
A method for manufacturing a semiconductor device, characterized in that, in a second pass, the remaining charge storage electrodes are formed at positions above the charge storage electrodes formed in the first pass.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2130252A JP2875588B2 (en) | 1990-05-22 | 1990-05-22 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2130252A JP2875588B2 (en) | 1990-05-22 | 1990-05-22 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0426156A true JPH0426156A (en) | 1992-01-29 |
| JP2875588B2 JP2875588B2 (en) | 1999-03-31 |
Family
ID=15029803
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2130252A Expired - Fee Related JP2875588B2 (en) | 1990-05-22 | 1990-05-22 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2875588B2 (en) |
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| JP2875588B2 (en) | 1999-03-31 |
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