JPH021732U - - Google Patents
Info
- Publication number
- JPH021732U JPH021732U JP7764688U JP7764688U JPH021732U JP H021732 U JPH021732 U JP H021732U JP 7764688 U JP7764688 U JP 7764688U JP 7764688 U JP7764688 U JP 7764688U JP H021732 U JPH021732 U JP H021732U
- Authority
- JP
- Japan
- Prior art keywords
- wiring pattern
- display substrate
- pattern structure
- substrate according
- transparent display
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 claims description 6
- 239000010408 film Substances 0.000 claims 2
- 239000004065 semiconductor Substances 0.000 claims 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 229920006015 heat resistant resin Polymers 0.000 claims 1
- 239000002184 metal Substances 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 claims 1
- 239000010409 thin film Substances 0.000 claims 1
Landscapes
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Description
第１図は本考案の実施例を示す要部拡大平面図
及び第２図は本考案の配線パターンを示すための
拡大平面図である。
１，１′……透明基板、２，２′……透明電極
、３，３′……配線パターン、４，４′……第１
及び第２の接合パツド。
FIG. 1 is an enlarged plan view of a main part showing an embodiment of the present invention, and FIG. 2 is an enlarged plan view showing a wiring pattern of the present invention. 1, 1'...Transparent substrate, 2, 2'...Transparent electrode, 3, 3'...Wiring pattern, 4, 4'...First
and a second joint pad.
Claims (1)
形成された表示領域と前記透明電極から延在され
所望形状の配線パターンの略先端部に設けられた
複数の第１の接合パツドに少なくとも１個の半導
体チツプがフエイスダウンボンデイングされる実
装領域とを有する表示用透明基板において、前記
半導体チツプは前記複数の第１の接合パツドから
延在形成された複数の第２の接合パツドに固着さ
れたことを特徴とする表示用透明基板の配線パタ
ーン構造。 (2) 前記第１の接合パツドから延在された第２
の接合パツドは少なくとも１個以上形成されたこ
とを特徴とする請求項１記載の表示用透明基板の
配線パターン構造。 (3) 前記第１及び第２の接合パツドを耐熱性樹
脂膜で区画することを特徴とする請求項１記載の
表示用透明基板の配線パターン構造。 (4) 前記配線パターン上には金属薄膜が設けら
れたことを特徴とする請求項１記載の表示用透明
基板の配線パターン構造。 (5) 前記第１及び第２の接合パツド間以外の領
域のみに前記金膜薄膜を設けたことを特徴とする
請求項４記載の表示用透明基板の配線パターン構
造。[Claims for Utility Model Registration] (1) A display area in which a plurality of transparent electrodes are formed to perform a desired display, and a plurality of display areas extending from the transparent electrodes and provided approximately at the tip of a wiring pattern having a desired shape. a mounting area in which at least one semiconductor chip is face-down bonded to the first bonding pads of the semiconductor chip; A wiring pattern structure of a transparent display substrate, characterized in that it is fixed to a second bonding pad. (2) a second joint pad extending from the first joint pad;
2. The wiring pattern structure of a transparent display substrate according to claim 1, wherein at least one bonding pad is formed. (3) The wiring pattern structure of a transparent display substrate according to claim 1, wherein the first and second bonding pads are separated by a heat-resistant resin film. (4) The wiring pattern structure of a transparent display substrate according to claim 1, wherein a metal thin film is provided on the wiring pattern. (5) The wiring pattern structure of a transparent display substrate according to claim 4, wherein the thin gold film is provided only in an area other than between the first and second bonding pads.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7764688U JPH0755540Y2 (en) | 1988-06-10 | 1988-06-10 | Wiring pattern structure of transparent substrate for display |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7764688U JPH0755540Y2 (en) | 1988-06-10 | 1988-06-10 | Wiring pattern structure of transparent substrate for display |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH021732U true JPH021732U (en) | 1990-01-08 |
| JPH0755540Y2 JPH0755540Y2 (en) | 1995-12-20 |
Family
ID=31302619
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7764688U Expired - Lifetime JPH0755540Y2 (en) | 1988-06-10 | 1988-06-10 | Wiring pattern structure of transparent substrate for display |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0755540Y2 (en) |
-
1988
- 1988-06-10 JP JP7764688U patent/JPH0755540Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0755540Y2 (en) | 1995-12-20 |
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