JPH0217518A - Data processor - Google Patents

Abstract

PURPOSE:To facilitate the cause investigation, etc., of an abnormal action by restarting a refreshing action before the data stored by a dynamic RAM are vanished even at the time of the generation of resetting. CONSTITUTION:For a data processor, a clock pulse 100 is inputted to a shift register 5 and a clock input terminal CK of a microprocessor 1 and an output signal 101 of a Schmitt trigger 4 and an output signal 102 of the processor 1 are inputted to a NAND gate 6. An output signal 103 of the gate 6 is inputted to a NAND gate 7 together with an output signal 104 of the shift register 5. After the resetting action of the above-mentioned dynamic RAM 2 of the microprocessor 1 is completed, the processor 1 is reset and the refreshing action of the RAM 12 is stopped. Thereafter, the said RAM 2, before the necessary refreshing period passes, releases the resetting of the above-mentioned processor 1 and the refreshing action of the RAM 2 is restarted before the memory contents are vanished.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a data processing device. More specifically, the present invention relates to the configuration of a novel data processing device having particular characteristics in its reset circuit.

BACKGROUND ART FIG. 3 is a block diagram showing a general configuration of a conventional data processing device using a microprocessor.

As shown in FIG. 3, this data processing device includes a bus 30
Processed unit 24 via a microprocessor 21, memory 22 and input/output interface 23 connected to
It is composed of etc. Further, the microprocessor 2I of this data processing device includes a signal line 201 for manually inputting a reset pulse.

FIG. 4 is a diagram showing a detailed configuration of the microprocessor 21, memory 22, and reset pulse signal line 201 in the data processing apparatus shown in FIG.

That is, as shown in FIG. 4, it is connected to the reset terminal R3T of the microprocessor 21,
The human-powered reset signal is a pulse generated by the reset switch 10 that is waveform-shaped by the Schmitt trigger 20, where the resistor R1 is a resistor that pulls up the reset switch, and the resistor R1 is a resistor that pulls up the reset switch.
2 and capacitor C2 constitute a filter for removing chattering noise of the reset switch.

On the other hand, the dynamic RAM forming the memory section 22 connected to the microprocessor 21 via the bus 300 is configured to be refreshed by a memory refresh signal 202 generated by the microprocessor 21.

In the data processing device configured as described above, when the reset switch is turned on to execute a system reset, a reset pulse with a width of a proportional shift pulse is applied to the microprocessor 21 at the time when the reset switch is turned on, and the microprocessor 21 is operated asynchronously. will be reset to That is, when the microprocessor 21 recognizes that the reset pulse signal 201 is active, it stops sending the dynamic RAM refresh signal 202, and then recognizes that the reset pulse signal 201 has returned to inactive. The transmission of the refresh signal 202 is restarted at the same time.

Problems to be Solved by the Invention In the conventional data processing device configured as described above, the pulse width of the reset pulse signal is determined in proportion to the closing time of the reset switch.

The actual input time is several hundred milliseconds or more, and is completely asynchronous and undefined with respect to the operating state of the microprocessor. In other words, in conventional data processing devices, it takes an undefined period of several hundred milliseconds or more after the reset pulse signal becomes active and the reset microprocessor stops the refresh signal until refresh is resumed. period was occurring.

On the other hand, the refresh synchronization necessary for the dynamic RAM to properly maintain its stored contents is constant, and the interval is generally within about 2 milliseconds, although it depends on conditions such as temperature. Therefore, if the above-mentioned reset is applied, the storage contents of the dynamic RAM will be destroyed. That is, it is highly unlikely that the storage contents of the dynamic RAM before the system reset will be properly stored and held even after the system reset.

Incidentally, it is often necessary to use a system reset in order to avoid abnormal operation of a data processing device caused by some reason.

In this case, the cause of the abnormal operation of the data processing device is analyzed by reading out the contents of the memory when the operation of the data processing device was abnormal, that is, the contents of the memory immediately before the system reset. There is a conventional method. However, as described above, in conventional information processing apparatuses, there is a problem in that such a method cannot be implemented because the stored contents of the memory are not retained by system reset.

SUMMARY OF THE INVENTION An object of the present invention is to solve the problems of the prior art described above and to provide a new data processing device configuration in which the storage contents of a dynamic RAM are retained even after a system reset is performed.

Means for solving the problem, that is, according to the present invention, a processing unit including a microprocessor, a processed unit controlled by the processing unit, and data executed between the processing unit and the processed unit Dynamic RAM that stores programs and data necessary for processing
A data processing device comprising a memory section including a memory section, further comprising a reset switch for externally resetting the processing section, and when the reset switch is turned on, a refresh operation of the dynamic RAM by the processing section is stopped; There is provided a data processing device characterized in that the stopped refresh operation is restarted before the stored memory contents are erased.

Effect: The data processing device according to the present invention enables the dynamic RAM to normally retain the memory contents before the microprocessor was reset, after the reset switch is turned on and the microprocessor is reset. The purpose is to provide a data processing device,
As a means of achieving this, the microprocessor's dynamic R
After the AM refresh operation is completed, the microprocessor is reset, thereby stopping the dynamic RAM refresh operation of the microprocessor, and then before the dynamic RAM has passed the refresh period necessary to retain its memory contents. In addition, the reset of the microprocessor is released, thereby making it possible to restart the dynamic RAM refresh operation of the microprocessor before the memory contents are erased.

The present invention will be described in more detail below with reference to the drawings, but what is disclosed below is only one embodiment of the present invention and does not limit the technical scope of the present invention in any way.

Embodiment FIG. 1 is a block diagram showing the configuration of a data processing apparatus according to the present invention.

As shown in FIG.
1 and the output signal 102 of the microprocessor 1 is NAN
Manpower is being sent to D Gate 6. Here, the output signal 102 of the microprocessor 1 is a signal pulse for refreshing the dynamic RAM 2;
2 is also man-powered.

Further, the output signal 103 of the NAND gate 6 is inputted to the NAND gate 7 together with the output signal 104 of the shift register 5, and the output signal 105 of the NAND gate 3 is inputted to the shift data terminal (SD) of the shift register 5.

Shift register 5 includes QASQB1Q6, QolQE
, QF, Qc, and QH output terminals, and outputs signals whose phases are sequentially shifted by a time equal to the period of the manually inputted clock pulse 100. Note that the signal 104 output from the QA output terminal is connected to the NAND signal as described above.
It is connected to one side of gate 7. Further, the signal 106 output from the Q6 output terminal is input to the reset signal input terminal (R3T) of the microprocessor I. Furthermore, the signal 107 output from the QH output terminal is connected to the clock pulse synchronous reset input terminal (R
3T). It is assumed that the output terminals QA, Qo and the input terminal (R3T) are of negative logic, and the others are of positive logic.

Microprocessor I and dynamic RAM 2 are coupled by an address data bus 200. In addition, resistor R3 is a pull-up resistor that supplies the power supply voltage (+Vcc) to resistor R2 when the set switch is not turned on, that is, when the oven is on, and resistor R2 and capacitor C8
This is a filter for removing chattering noise from the signal produced by the beam set switch, and is further provided with a Schmitt trigger 4. Here, the circuit composed of resistor R1, resistor R2, capacitor C1, and Schmitt trigger 1 is a general circuit for shaping the waveform so that the subsequent logic circuit does not cause malfunction, and is a conventional circuit for shaping the waveform so that the logic circuit in the subsequent stage does not malfunction. It has the same configuration as the reset circuit of , and may have any other configuration.

FIG. 2 shows each signal line 1 in the circuit shown in FIG.
It is a time chart showing signal waveforms of 00 to 107.

In FIG. 2, Tl represents the cycle from when the microprocessor 1 of the circuit shown in FIG. The period may actually be longer than TI. Further, T2 indicates that after the signal 106 input to the reset signal input terminal (RS T) of the microprocessor 1 makes a state transition from logic "1" to logic 1101+ (that is, reset release), the microprocessor 1 is reset for the first time. This is the time required to output the refresh signal 102.

Below, with reference to FIG. 2, the operation at the time of reset of the data processing apparatus according to the present invention shown in FIG. 1 will be explained.

When the reset switch 3 is turned on, the output signal 101 of the Schmitt trigger 4 changes from logic II OI+ to logic "1".
Transition to. Here, the signal 101 is connected to one input of the NAND gate 6;
The other input is connected to the reflexo signal 102 of the microprocessor 5, so when the signal 102 changes state from logic "0" to logic "behavior" after a predetermined time has elapsed, the signals 101 and 102 The output signal 103 of the NAND gate 6, which is the negation of the logical sum of The signal 104 indicates that the clock pulse signal 100 is still at logic "0".
Since this is before the state transition from to logic ``1'', logic BI is maintained. Therefore, the output signal 105 of the NAND gate 7, which is the negation of the logical sum of the signal 103 and the signal 104, is
The state transitions from logic "o" to logic "1". Thus, the output signal 10 of the output terminal QE of the shift register 5
6 is shifted by a prescribed phase, and as shown in FIG. 2, the synchronous 4y2 period phase of the signal 100 is shifted with respect to the signal 105, and the state transitions from logic "0" to logic +1111.Here, , the signal 106 outputs a reset signal from the reset signal input terminal (R3T) of the microprocessor 1, the microprocessor 1 is reset, and thereafter the signal 102 for refreshing the dynamic RAM 2 is not output until the reset is released.

On the other hand, the output signal 10 of the output terminal Qo of the shift register 5
7 is the logic II O11 of the signal 106 to the logic 1
In response to the state transition to ``, the phase of three cycles of the signal 100 is shifted, and the state transitions from the logic n 1 u to the logic ``0'', and the signal 107 is applied to the clock pulse signal synchronization reset terminal (R3T) of the shift register 5. ), all outputs are reset in synchronization with the state transition of the signal 100 from logic "0" to logic "1". Therefore, the signal 106 also changes from logic "1" to logic "0"
The state transitions to dynamic R of microprocessor 1.
The output of the signal 102 that refreshes AM2 is resumed.

In this way, in the circuit shown in FIG. 1, no matter what timing the reset switch 3 is turned on,
The time from the completion of the last refresh before the microprocessor 1 is reset until the reset is released and the refresh is restarted is fixed at T1, as shown in FIG. Here, as mentioned above, the refresh cycle required for the dynamic RAM 2 to properly retain its memory contents is longer than Tl, so the dynamic RAM 2 normally retains the memory contents immediately before the microprocessor 1 is reset. There is.

By the way, in this embodiment, the signal 106 for resetting the microprocessor 1 and the signal 107 for resetting the shift register 5 are extracted from QE and Q)I of the shift register 5, but these can be set freely. , it goes without saying that the above-mentioned TI can also be set arbitrarily.

Effects of the Invention As detailed above, the data processing device according to the present invention is configured to restart the refresh operation before the data stored in the dynamic RAM disappears even when a reset is applied. The data stored in the dynamic RAM immediately before can be read correctly even after reset. Therefore, it is possible to easily investigate the cause of abnormal operation of the data processing device before resetting.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a configuration example of a data processing device according to the present invention, FIG. 2 is a time chart for explaining the operation of the device shown in FIG. 1, and FIG. , is a block diagram showing the general configuration of a conventional data processing device using a microprocessor, and FIG. 4 shows a detailed configuration of the data processing device shown in FIG. FIG. [Main reference numbers] L21... Microprocessor, 2.22... Dynamic RAM. 3.10... Reset switch, 4.20... Schmitt trigger, 5... Shift register, 23... Input/output interface, 24...
Processed part, 201106...Reset signal line. 2Ω2...Refresh signal line, 203...Clock pulse signal line, 200.3
00... bus

Claims (1)

[Scope of Claims] A processing section including a microprocessor, a processed section controlled by the processing section, and a program and data necessary for data processing executed between the processing section and the processed section. A data processing device comprising a memory unit including a dynamic RAM that performs the processing, further comprising: a reset switch for externally resetting the processing unit, and when the reset switch is turned on, a refresh operation of the dynamic RAM by the processing unit is stopped; A data processing device characterized by being configured to restart the stopped refresh operation before the memory contents stored in the dynamic RAM are erased.