JPH046024B2 - - Google Patents

Description

Detailed Description of the Invention (Description of the Technical Field) The present invention relates to a microprogram tracing device used in a microprogram control device, and more specifically, a microprogram tracing device for tracing the execution of a microprogram in a microprogram tracing device. Regarding.

(Description of the Prior Art) Conventional tracers have a finite storage capacity, and therefore, when the number of steps in a microprogram is extremely large, the storage capacity is exceeded and continuous tracing cannot be performed.

(Description of the purpose of the invention) The purpose of the present invention is to stop the clock when the storage space in the internal storage device runs out, and restart the clock again when the output of data in the internal storage device is completed, so that tracing can be executed intermittently. The object of the present invention is to provide a microprogram tracing device which solves the above-mentioned drawbacks by doing the following.

(Description of Structure and Effects of the Invention) A microprogram trace device according to the present invention includes an address register, an internal storage device, and at least first and second control means. The address register receives the external microprogram address and clock and applies it to internal storage.

Internal storage stores this microprogram address in synchronization with the clock.

When the internal storage device has stored the microprogram addresses up to its maximum capacity, the first control means stops the clock of the external microprogram control device and transfers the internal storage to an external output device or external storage device. Output data from the device.

When data output from the internal storage device is completed, the second control means restarts the clock of the external microprogram controller and also restarts writing to the internal storage device.

In addition to the basic configuration described above, the microprogram tracing device according to the present invention can be provided with a trace start address instructing means and a control means, a trace end address instructing means and a control means, and the microprogram address value is continuously the same. It is also possible to provide means for inhibiting writing even when the value is taken, and counting the number of clocks during the inhibit period.

Furthermore, when a conditional branch instruction is executed by an external microprogram controller,
It is also possible to store only the microprogram address after execution in the internal storage device.

It is also possible to provide means for storing the microprogram address at the checkpoint in the internal storage device when the external microprogram controller passes the checkpoint.

(Description of Examples) Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of a microprogram tracing device according to the present invention. In FIG. 1, the microprogram trace device has an address register 1 and an internal storage device 2.
, a counter 4, and first to third delay circuits 5,
7, 13 and the first to fifth AND gates 8, 9,
10, 14, 15, first to third OR gates 6, 11, 16, and first flip-flop 12
It is established from .

The address register 1 receives a microprogram address sent from an external microprogram controller via a microprogram address signal line 100.

Internal storage 2 stores the microprogram address being traced. Counter 4 controls the trace operation of internal storage device 2. 1st~
The third delay circuits 5, 7, 13 and the first to fifth delay circuits 5, 7, 13,
AND gates 8, 9, 10, 14, 15 and the first
~The third OR gates 6, 11, and 16 are integrated with the counter 4 and control the trace operation of the internal storage device 2.

A first flip-flop 12 controls writing and reading data in internal storage.

Next, the operation of the first embodiment of the microprogram tracing device according to the present invention will be explained with reference to FIG. First, in order to start up this device, a device power-on completion signal or an external trace start instruction signal is applied to the startup signal line 101, thereby resetting the counter 4, and
The first flip-flop 12 is set and trace operation begins.

That is, the microprogram address appearing on the microprogram address signal line 100 is set in register 1 in synchronization with the clock appearing on the first clock signal line 101 from the microprogram controller. At this time, the clock appearing on the first clock signal line 101 is appropriately delayed through the second delay circuit 7, and the clock appearing on the first AND
is applied to the input terminal of gate 8.

At the same time, the signal appearing on the positive output signal line 110 of the first flip-flop 12 is the first AND signal.
is applied to the other input terminal of gate 8.

The logical product of these signals is connected to the first AND gate 8.
It can be obtained with Therefore, the signal appearing on the output signal line 109 becomes a write instruction signal to the internal storage device 2, and the signal appearing on the output signal line 103 of the register 1 is written to address 0 of the internal storage device 2. . Further, the counter 4 is incremented by the signal passing through the fifth AND gate 15, the first delay circuit 5, and the third OR gate 16 and appearing on the clock signal line 107. Then, address number 1 is specified.

In this way, the microprogram addresses are sequentially written into the internal storage device 2.

When the writing space in the internal storage device 2 runs out, the address area of the counter 4 overflows and an overflow pulse signal is output onto the signal line 105. When a pulse appears on the signal line 105, the state of the output of the first OR gate 6 becomes 1 and the counter 4 is reset. At this time, the
A 3AND gate 10 performs a logical product between the input of the first OR gate 6 and the positive output of the first flip-flop 12. When the first flip-flop 12 is reset, no write pulse is output on the signal line 109, and writing to the internal storage device 2 is inhibited. Further, a pulse signal is output to the microprogram control device on signal line 113 to instruct the microprogram control device to stop the clock. The fourth AND gate 14 performs an AND operation between the signal appearing on the second clock signal line 115 and the negative output of the first flip-flop 12.

Therefore, the counter 4 is counted up by the signal inputted via the third delay circuit 13 and the third OR gate 16. An external output device or an external storage device operates in synchronization with the clock on the second clock signal line 115 and captures the information on the output signal line 104.

This information is output to a printer, display device, or other storage device.

When the output to the outside is completed, the address of the counter 4 overflows and an overflow pulse signal is output onto the signal line 105.

When an overflow pulse signal is output on the signal line 105, the counter 4 is reset, and the signal on the signal line 105 and the first flip-flop 1 are
The logical product with the negative output of 2 is the second AND gate 9
is required. The output of the second AND gate 9 is applied to the first flip-flop 12 via the second OR gate 11 to set the first flip-flop 12. , along with this, the signal line 11
A pulse signal is output on 2 to send a clock restart instruction signal to the microprogram controller.

As described above, microprogram address tracing operations can be performed continuously.

Next, a second embodiment of the microprogram tracing device according to the present invention is shown in FIG.

The second embodiment will be explained with reference to FIGS. 1 and 2. The microprogram tracing device in FIG. 2 includes an address register 1, an internal storage device 2, and first and second matching circuits 1.
7 and 18, a second flip-flop 19, and sixth and seventh AND gates 20 and 21. In the second embodiment, when the trace start address signal instructed from the outside via the trace start address signal line 120 and the output signal of the address register 1 match, the state of the output on the signal line 122 becomes 1. Become. Signal line 102 in FIG.
Instead of the above signal, the output signal on signal line 122 sets the first flip-flop 12 and resets the second flip-flop 19.

Hereinafter, the second embodiment operates in the same way as the first embodiment. That is, when a trace stop signal is externally sent onto the trace stop address signal line 121 and the output of the address register 1 matches this signal, the state of the signal on the signal line 123 becomes 1. Therefore, this signal is connected to signal line 1 in Figure 1.
The resulting logical OR is used to reset the first flip-flop 12 and set the second flip-flop 19.

Further, the clock stop signal on the clock stop signal line 113 and the clock restart signal on the clock restart signal line 112, which are sent to the microprogram controller, are outputted to the second clock by the sixth and seventh AND gates 20 and 21, respectively. Synchronization is achieved by performing an AND with the negative output of the flip-flop 19, and the signal line 11
20, 1130 to the outside.

Next, a third embodiment of the microprogram tracing device according to the present invention is shown in FIG.

The third embodiment will be explained with reference to FIGS. 1 and 3. The microprogram tracing device in FIG. It is established from

In the third embodiment, when the same address appears consecutively, writing to the internal storage device 2 is inhibited and address updating is also inhibited. That is, when the state of the signal appearing on the mismatch signal line 124 is 1, the output of the address register 1 is set to the buffer register 22. When the state of the signal appearing on the mismatch signal line 124 becomes 0, the output of the tenth AND gate 88 becomes the state 0. At this time, the signal on the address update signal line 119 is suppressed by the ninth AND gate 25. , the state of the output appearing on the signal line 107 becomes 0, and writing to the internal storage device and counting up of the counter 4 are inhibited.

Next, when the system is notified that a branch instruction has been executed, the output of the first AND gate 8 in FIG. 1 and the signal on the address update signal line 119 are enabled one clock after the notification. Just connect to. Furthermore, if passage through a checkpoint is instructed, the signals on the first AND gate 8 and the address update signal line 119 may be enabled at the timing corresponding to the notified address. .

(Description of Effects of the Invention) As explained above, the present invention has the following features: When there is no more writing space in the internal storage device, the microprogram controller is instructed to stop the clock, and the contents of the internal storage device are read out. By arranging the structure so that restarting the clock can be instructed after the clock has finished, tracing of consecutive addresses can be easily performed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of a microprogram tracing device according to the present invention, and FIG.
FIG. 3 is a block diagram partially showing a second embodiment of the microprogram tracing device according to the present invention, and FIG. 3 is a block diagram partially showing a third embodiment of the microprogram tracing device according to the present invention. 1... Address register, 2... Internal storage device, 4... Counter, 5, 7, 13... Delay circuit, 6, 11, 16... OR gate, 8, 9, 1
0, 14, 15, 20, 21, 24, 25, 88
...AND gate, 12, 19...flip-flop, 17,18,23...matching circuit, 22...
Batsuhua register.

Claims (1)

[Scope of Claims] 1: an address register for receiving a microprogram address and a clock from an external microprogram control device; an internal storage device for storing the microprogram address in synchronization with the clock; When the storage device has stored the microprogram addresses to its maximum capacity, the clock of the external microprogram control device is stopped and the data is outputted from the internal storage device to an external output device or an external storage device. a first control means for generating a trace stop signal when outputting data from the internal storage device; restarting a clock of the external microprogram controller when data output from the internal storage device is completed; and second control means for generating a trace start signal to restart the trace. 2. The microprogram tracing device according to item 1, characterized in that it comprises first instruction means for instructing a trace start address. 3. The microprogram tracing device according to item 1, characterized in that it comprises second instruction means for instructing a trace end address. 4. The microprogram tracing device according to item 1 above, further comprising third control means for inhibiting writing to the internal storage device when the value of the microprogram address continuously takes the same value. A microprogram tracing device characterized by: 5. The microprogram tracing device according to the above item 1 or 4, comprising a fourth control means for calculating and outputting a count value of the number of consecutive clocks during the period in which the storage is inhibited. A microprogram tracing device characterized by: 6. In the microprogram tracing device according to the above item 1, when the external microprogram control device notifies that the conditional branch instruction has been executed, the microprogram after executing the conditional branch instruction. A microprogram tracing device comprising fifth control means for storing only addresses in the internal storage device. 7. The microprogram tracing device according to item 1 above, which stores only the microprogram address at the checkpoint in an internal storage device when notified from the external microprogram control device that a checkpoint has been passed. A microprogram tracing device characterized by comprising sixth control means for. 8. The microprogram tracing device according to item 1 above, characterized by comprising a seventh control means for starting tracing upon receiving the trace start signal from the external microprogram control device. Microprogram trace device. 9. The microprogram tracing device according to item 1 or 8, further comprising an eighth control means for stopping the tracing in response to the trace stop signal from the external microprogram control device. Features: Microprogram tracing device.