JPH0217835A - Power unit equipped with back-up power supply - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a power supply device equipped with a backup power source, and in particular, a power supply device that increases the retention time for storing and retaining data stored in a volatile memory using a backup power source. related to things.

[Prior art]

-i.In electronic devices such as electronic typewriters, word processors, and electronic notebooks, when the power switch is on, current from the main power supply is supplied to volatile memory such as static RAM, and the data is stored in this volatile memory. Some electronic devices are equipped with a backup power source so that important data stored in volatile memory can be continuously stored even when the power switch of the electronic device is turned off. .

For example, a power supply circuit equipped with a backup power supply is configured as shown in FIG. 6, and when the power switch 30 is turned on, current from the main power supply E3 is supplied to the RAM 32 via the voltage stabilization circuit 31. The data stored in the RAM 32 is stored and held. Also, power switch 3
0 is turned off, current flows from the backup power source E4 (primary battery) such as a lithium battery to the RAM3.
2, and the data in the RAM 32 is continuously stored and held.

[Problem to be solved by the invention]

As the voltage stabilizing circuit 31, a one-chip three-terminal regulator element is generally used, and this regulator element is composed of a large number of semiconductors, resistors, and the like. Therefore, when the power switch 30 is turned off and a predetermined voltage is not applied to the input terminal 31a of the voltage stabilizing circuit 31, the output terminal 31C and the reference voltage terminal 31b are connected due to the connection relationship of semiconductors, resistors, etc. In many cases, the voltage stabilizing circuit 31 is electrically connected via a resistor.

In such a case, the output terminal 31 of the voltage stabilizing circuit 31
Since the voltage of backup power supply E4 is applied to c,
A current i4 flows from the bank amplifier power supply E4 to the RAM 32, while a current i5 flows from the backup power supply E4 through the reference voltage side connection circuit L++ of the voltage stabilization circuit 31.

In this way, since the current i5 flows backward from the backup power source E4, there is a problem that the hack-up power source E4 is consumed in a short period of time.

Therefore, as shown in FIG. 7, a diode D3 is interposed between the output terminal 31c of the voltage stabilizing circuit 31 and the cathode terminal of the diode D2 to prevent the current i5 from flowing backward from the reference voltage side connection circuit LR. It is also possible. but,
When the diode D3 is provided in this way, when the load of the RAM 32 changes when the power switch 30 is turned on, a voltage drop occurs due to the diode D3, and the RAM
A problem arises in that a stable voltage cannot be supplied to 32.

SUMMARY OF THE INVENTION An object of the present invention is to provide a power supply device equipped with a pack amplifier power supply that can supply a stable voltage from a main power supply to a volatile memory and prevent leakage of current from a backup power supply.

[Means to solve the problem]

As shown in the configuration diagram of FIG. 1, a power supply device equipped with a backup power supply according to the present invention includes a main power supply that supplies current to a volatile memory via a voltage stabilization circuit when a power switch is ON; In a power supply device equipped with a bank amplifier power supply that supplies current to volatile memory when the power switch is OFF, the connection circuit between the input side of the voltage stabilizing circuit and the reference voltage side when the power switch is OFF. A cutoff circuit is provided to cut off at least the connection circuit on the reference voltage side of the circuit, and the current from the backup power supply is configured to prevent the current from flowing back into the ground line through the voltage stabilization circuit and the connection circuit on the reference voltage side. This is what I did.

Incidentally, the switch section of the above-mentioned cutoff circuit is composed of a beam race inch, a semiconductor switching element, and the like.

[Effect]

In the power supply device equipped with a backup power source according to the present invention, when the power switch is ON, the connection circuit at the input end of the voltage stabilization circuit and the connection circuit on the reference voltage side are not cut off, so the voltage stabilization circuit is activated. The main power supply then supplies current to the volatile memory via the power switch and voltage stabilization circuit.

Therefore, data stored in volatile memory is retained.

When the power switch is turned off, at least the reference voltage side connection circuit of the input side connection circuit and the reference voltage side connection circuit of the voltage stabilizing circuit is cut off. This results in
Since current is supplied from the backup power supply to the volatile memory, data in the volatile memory is continuously stored and held.

Here, a one-chip three-terminal regulator element is generally used as the voltage stabilizing circuit, and this regulator element is composed of a large number of semiconductors, resistors, and the like. Therefore, when the power switch is turned off and a predetermined voltage is not applied to the input terminal of the voltage stabilizing circuit, the output terminal and the reference voltage terminal may be connected to each other within the voltage stabilizing circuit due to the connection of semiconductors, resistors, etc. In many cases, there is electrical continuity through a resistor. However, since the cutoff circuit cuts off at least the connection circuit on the reference voltage side of the voltage stabilization circuit, the flow of current from this connection circuit is prevented. Note that the reverse flow of current from the backup power source to the main power source via the voltage stabilizing circuit and its input side connection circuit is prevented by turning off the power switch. Furthermore, when the power switch is not interposed between the main power source and the voltage stabilizing circuit, it is desirable that the cut-off circuit also cut off the connection circuit on the input side of the voltage stabilizing circuit. As a result, the power of the backup power source is only consumed by the volatile memory for backup purposes.

Furthermore, since the output side terminal of the voltage stabilization circuit is directly connected to the volatile memory, the output of the voltage stabilization circuit remains unchanged even if the load changes when accessing or backing up the volatile memory when the power switch is turned on. Voltage does not fluctuate.

〔Effect of the invention〕

According to the power supply device including the backup power supply according to the present invention, when the power switch is turned off, at least the connection circuit on the reference voltage side of the voltage stabilizing circuit is cut off, so that the connection circuit from the backup power supply to the reference voltage side is cut off. The reverse flow of current flowing to the ground line through the ground line is prevented. Therefore, since the power of the backup power source is consumed only for backing up the volatile memory, the backup time of the backup power source can be significantly increased.

In addition, the connection circuit on the output side of the voltage stabilization circuit is directly connected to the volatile memory without intervening a diode, and a stable voltage is applied to the volatile memory even if the load fluctuates when the power switch is turned on. Therefore, the data stored in the volatile memory can be reliably stored and retained.

〔Example〕

Embodiments in which the present invention is applied to an electronic notebook will be described below with reference to the drawings.

The electronic notebook l that stores addresses, names, telephone numbers, and other information includes a keyboard 2, a liquid crystal display mechanism 3, a control device C, a power supply circuit 4, etc., as shown in the block diagram of the control system in Fig. 2. We are prepared.

The keyboard 2 is provided with character keys and numeric keys for inputting data, as well as various function keys. The liquid crystal display mechanism 3 is a general mechanism that includes a display made of a liquid crystal display and a display controller that outputs a drive signal to the display.

The control device C includes a 1-chip CPU (central processing unit) 5 and an RO connected to the CPtJ5 via a data bus or the like.
M (read-only memory) 6 and static R
RAM (random) consisting of volatile memory such as AM
The keyboard 2 and the liquid crystal display mechanism 3 are each connected to the CPU 5.

As shown in FIG. 3, the power supply circuit 4 includes a main power supply E1, a backup power supply E2, a voltage stabilization circuit 12, and a cutoff circuit 1.
3, keyboard 2, liquid crystal display mechanism 3, CPU 5
, supplies predetermined voltages to ROM 6 and RAM 7, respectively, and also supplies backup power E when power switch 8 is turned off.
2 stores and holds data in each memory of the RAM 7.

The ROM 6 stores a control program that controls the liquid crystal display mechanism 3 in response to code data input from each key of the keyboard 2, a search control program that searches for a telephone number, etc. based on input data such as a name, etc. ing.

The RAM 7 is provided with a data memory for storing input names, addresses, telephone numbers, and other information, and various types of memories for temporarily storing results of arithmetic processing by the CPU 5.

Next, the power supply circuit 4 provided with a backup power supply will be explained based on FIG. 3.

A power switch 8 and a main power source E1 having a predetermined voltage (for example, 5V) are connected in series and are interposed between a terminal 10 and a terminal 11 connected to a ground line 14.

Further, the terminal IO is connected to one terminal 9a of the auxiliary switch 9. The power switch 8 and the auxiliary switch 9 are interlocked, and are configured to open or close in synchronization. The input terminal 12a of the voltage stabilizing circuit 12 is connected to the input side connection circuit L1.
A transistor TRI (switching element) is provided in the middle of the connection circuit L1, the collector of the transistor TRI is connected to the input terminal 12a, and the emitter of the transistor TRI is connected to the terminal 10. has been done.

The output terminal 12c of the voltage stabilizing circuit 12 is connected to the terminal Vcc of the RAM 7 via the output side connection circuit L3. Note that the terminal GND of the RAM 7 is connected to the ground line 14. Also, the reference voltage terminal 12 of the voltage stabilizing circuit 12
b is connected to the ground line 14 via the connection circuit L2 on the reference voltage side.
and a transistor T is connected in the middle of the connection circuit L2.
R3 is provided, the collector of the transistor TR3 is connected to the reference voltage terminal 12b, and the collector of the transistor TR3 is connected to the reference voltage terminal 12b.
The emitter of No. 3 is connected to the ground line 14.

The base of the transistor TRI is connected to the collector of the transistor TR2 via the resistor R2, and the base of the transistor TR
The emitter of the transistor TR2 is connected to the ground line 14, and the base of the transistor TR2 is connected to the other terminal 9b of the auxiliary switch 9 via a resistor R4. The base of the transistor TR3 is connected to the terminal 9b of the auxiliary switch 9 via a resistor R6. Also, the transistor TRI
A resistor R1 is interposed between the emitter and the base of the transistor TR2, a resistor R3 is interposed between the emitter and the base of the transistor TR2, and a resistor R5 is interposed between the emitter and the base of the transistor TR3.

A hack-a-knob power source E2 consisting of a diode DI, a resistor R7, and a lithium battery is connected in series between the connection point 7a in the middle of the connection circuit L3 on the output side and the ground line 14, as shown in the figure. .

This backup power source E2 is a primary battery with an output voltage of about 3.

The voltage stabilizing circuit 12 is an l-chip three-terminal regulator element having an input terminal 12a, a reference voltage terminal 12b, and an output terminal 12C, and is composed of a plurality of transistors, resistors, and the like. Resistor R7 is backup power supply E2
It is a limiting resistor to limit the amount of current flowing out from the
The diode Dl prevents current from flowing backward into the backup power source E2. Transistor TRI, transistor TR2, transistor TR3, and resistors R1 to R6
This constitutes a cutoff circuit 13. Note that the main power source El supplies power to the CPU 5 , ROM 6 , keyboard 2 , and liquid crystal display mechanism 3 via the power switch 8 .

Next, the operation of the power supply circuit 4 will be explained.

First, to explain the effect of supplying current from the main power source El to the RAM 7 when the power switch 8 is turned on, when the power switch 8 is turned on, the auxiliary switch 9 is also turned on, and at the same time the resistor R6 and The voltage applied to the voltage dividing point of the resistor R5 causes the base current of the transistor TR3 to flow, making the transistor TR3 conductive. Thereby, the reference voltage terminal 12b of the voltage stabilizing circuit 12 is connected to the ground line 14 via the reference voltage side connection circuit L2, and the reference voltage of the voltage stabilizing circuit 12 is set.

Furthermore, the base current of the transistor TR2 flows due to the voltage applied to the voltage dividing point between the resistor R4 and the resistor R3, and the transistor TR2 becomes conductive. When the transistor TR2 becomes conductive, the base current of the transistor TR1 flows due to the voltage applied to the voltage dividing point between the resistor R2 and the resistor R1, and the transistor TRI becomes conductive. Therefore, the output voltage of the main power supply El is applied to the input terminal 12a of the voltage stabilization circuit 12 via the power switch 8 and the input side connection circuit L1, and the stable voltage output from the output terminal 12c is applied to the output side. is applied to the terminal Vcc of RAM7 via the connection circuit L3,
Current is supplied to the RAM 7 and data is stored and held.

Note that since the output terminal 12c of the ONN lightning voltage stabilizing circuit 12 of the power switch 8 and the terminal Vcc of the RAM 7 are directly connected through the connection circuit L3 on the output side, the load when storing data in the RAM 7 may fluctuate. Also, there is no fluctuation in the voltage output from the output terminal 12c, and the data is reliably stored and held.

Next, to explain the effect of supplying current from the backup power source E2 to the RAM 7 when the power switch 8 is turned OFF, when the power switch 8 is turned OFF, the auxiliary switch 9 is also turned OFF. At the same time,
Since the transistor TR3 is turned off, the connection circuit L2 on the reference voltage side is cut off.

Furthermore, since the transistor TRI is also turned off as the transistor TR2 is turned off, the voltage stabilizing circuit 12
The connection circuit L1 at the input end of is cut off. As a result, no current is supplied from the main power supply El to the RAM7 (but at this time, the backup voltage of the backup power supply E2 is applied to the terminal Vcc of the RAM7 via the connection point 7a,
7 is supplied with current from the backup power supply E2,
The data will not be erased (it will continue to be stored and retained).

Therefore, even if the power switch 8 is turned off and no predetermined voltage is applied to the input terminal 12a of the voltage stabilizing circuit 12, the output terminals 12c, ! : The reference voltage terminal 12b is often electrically connected to the voltage stabilizing circuit 12 via a resistor.

but,? When the ft & switch 8 is OFF, the connection circuit L2 on the reference voltage side and the connection circuit L1 on the input side are respectively cut off, so that the current does not flow backward from the backup power supply E2 through the voltage stabilization circuit 12, and the current 11 Is it RAM?
It just flows to. As a result, the backup power supply E
Since the power of E2 is only consumed by the RAM 7 for backup purposes, the power consumption of the backup power source E2 can be reduced as much as possible, and the backup time of the bank amplifier type R2 can be significantly extended.

The power supply circuit 4 equipped with the backup power supply is partially modified as shown in FIG.
A power supply equipped with a backup power supply in which a delay timing signal generation circuit 15 is provided between the resistor R4 and the resistor R6, and the voltage stabilization circuit 12 operates more reliably when the power switch 8 is turned on. A circuit 4A may also be configured.

Next, this delayed timing signal generation circuit 15 will be explained.

A terminal 9b of the auxiliary switch 9 is connected to the heel of the transistor TR4 via a connecting circuit L4 having a resistor R8.
The collector of the transistor TR4 is connected to the positive terminal of the Doryu 1p+ via a connection circuit L5 having a pull-up resistor RIO with a sufficiently large resistance value, and a capacitor C1 and a resistor R9 are connected between the base of the transistor TR4 and the terminal 11.
are connected in parallel. The collector of the transistor TR4 is connected to the emitter of the transistor TR4 via a Schmitt trigger inverter 16, a Schmitt trigger amplifier 17, a resistor R11, and a capacitor C2. Also, transistor TI? 4 and the capacitor C2 are grounded. The output terminal of the inverter 16 is connected to one input terminal of an AND gate 19 and one input terminal of an OR gate 20.
The other input terminal of the gate 19 and the other input terminal of the OR gate 1-20 are connected to the connection point between the capacitor C2 and the resistor R11 via a Schmino rigger type amplifier 18 and a resistor R12. The output terminal of the AND gate 19 is connected to the resistor R4 via the connecting circuit L6, and the output terminal of the OR gate 20 is connected to the resistor R6 via the connecting circuit L7.

Next, the operation of generating two different timing signals in the delayed timing signal generation circuit 15 will be explained based on FIGS. 4 and 5.

When the power switch 8 is OFF, the auxiliary switch 9 is also OFF.
Since the transistors are FFs, all of the transistors TRI to TR4 are not conductive. Here, when the power switch 8 is turned on at time tl, the auxiliary switch 9 is also turned on at the same time, and the capacitor C1 is charged with the voltage applied to the voltage dividing point of the resistor R8 and the resistor R9, and the base of the transistor TR4 is charged. When the applied voltage gradually increases and reaches a predetermined voltage after a predetermined delay time τ1, the base current of the transistor TR4 flows and the transistor TR4 becomes conductive. At this time, as the collector voltage of the transistor TR4 becomes "L" level, an rHJ level signal is output from the inverter 16, and at time L2 delayed by a predetermined time τl from time L1, one of the OR gates 20 is output. The HJ level signal is input to the input terminal, the rHJ level signal is output from the output terminal of the OR gate 20, and the transistor T
, R3 are conductive. At this time, the rHJ level signal and the rLJ level signal are input to the input terminal of the AND gate 19, and the rLJ level signal is output from the output terminal of the AND gate 19.

The capacitor C2 is gradually charged by the "T" level signal output from the inverter 16, and when it reaches a predetermined voltage after a predetermined delay time 2, the rI-(J level signal is output, and at time t3 delayed by a predetermined time τ2 from time t2, AND gate 1
An "I(" level signal) is output from the output terminal of the transistor 9, and the transistor TR2 and the transistor TRI are respectively set to ia.

In this way, first, as the transistor TR3 becomes conductive, the connection circuit L2 on the reference voltage side of the voltage stabilizing circuit 12 becomes conductive, and the reference voltage terminal 12b is connected to the ground line 14, and after a predetermined time, the transistor TRI becomes conductive. Along with the conduction, the connection circuit L1 on the input side of the voltage stabilizing circuit 12 becomes conductive and the voltage of the main power supply E1 is applied to the input terminal 12a, so that a stable voltage is output from the output terminal 12C of the voltage stabilizing circuit 12. Voltage is reliably output.

Note that only the connection circuit L2 on the reference voltage side of the voltage stabilizing circuit 12 may be cut off. Further, the connection circuit LL on the input side and the connection circuit L2 on the reference voltage side may be respectively cut off by a relay switch or a switch that opens and closes in conjunction with the power switch 8.

Note that the backup power source E2 may be configured with a secondary battery and a charging circuit may be added. It goes without saying that the present invention can also be applied to various electronic devices such as electronic typewriters and word processors equipped with a backup power source.

[Brief explanation of the drawing]

The drawings show embodiments of the present invention; Fig. 1 is a block diagram of the invention, Fig. 2 is a block diagram of the control system of the electronic notebook, and Fig. 3 is a block diagram of the control system of the electronic notebook.
The figure is a circuit diagram of a power supply circuit equipped with a hack-up power supply, FIG. 4 is a circuit diagram of a power supply circuit equipped with a backup power supply according to a modification of the present invention, and FIG. 5 is an operation in the power supply circuit of FIG. 4. The time chart and FIGS. 6 and 7 are circuit diagrams of a power supply circuit equipped with a backup power supply according to the prior art, respectively. 7. Squitty RAM, 8. Power switch 8
, 9... Auxiliary switch 9, 12... Voltage stabilization circuit 12
, 13... Cutoff circuit 13, El... Main power supply, E2
...Backup power supply, TRI~TR4...transistor. Patent applicant Brother Industries, Ltd.

Claims (1)

[Claims] (1) A main power supply that supplies current to the volatile memory via a voltage stabilization circuit when the power switch is ON, and a backup power supply that supplies current to the volatile memory when the power switch is OFF. In the power supply device, a cutoff circuit is provided that cuts off at least a reference voltage side connection circuit of an input side connection circuit and a reference voltage side connection circuit of the voltage stabilizing circuit when the power switch is turned off, and the backup circuit 1. A power supply device equipped with a backup power supply, characterized in that the power supply device is configured to prevent the current of the power supply from flowing backward through the voltage stabilization circuit.