JPH0217839U - - Google Patents
Info
- Publication number
- JPH0217839U JPH0217839U JP1988096284U JP9628488U JPH0217839U JP H0217839 U JPH0217839 U JP H0217839U JP 1988096284 U JP1988096284 U JP 1988096284U JP 9628488 U JP9628488 U JP 9628488U JP H0217839 U JPH0217839 U JP H0217839U
- Authority
- JP
- Japan
- Prior art keywords
- conductor layer
- integrated circuit
- layer
- hybrid integrated
- insulating substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
- H10W72/07551—Controlling the environment, e.g. atmosphere composition or temperature characterised by changes in properties of the bond wires during the connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/59—Bond pads specially adapted therefor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
- H10W72/932—Plan-view shape, i.e. in top view
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Wire Bonding (AREA)
Description
第１図は本考案の一実施例を示す混成集積回路
の断面図、第２図は従来の混成集積回路を示す断
面図である。
１……セラミツク基板、２……導体層、３……
層間絶縁層、４……導体層、５……層間絶縁層、
６……導体層、７……ボンデイング線。
FIG. 1 is a sectional view of a hybrid integrated circuit showing an embodiment of the present invention, and FIG. 2 is a sectional view of a conventional hybrid integrated circuit. 1...Ceramic substrate, 2...Conductor layer, 3...
interlayer insulating layer, 4... conductor layer, 5... interlayer insulating layer,
6... Conductor layer, 7... Bonding wire.
Claims (1)
、前記導体層を被覆して設けたポリイミド樹脂か
らなる絶縁層とを積層してなる混成集積回路にお
いて、前記絶縁基板上に設けた第１層の導体層に
設けたボンデイングパツドを有することを特徴と
する混成集積回路。 In a hybrid integrated circuit formed by laminating a conductor layer patterned on an insulating substrate and an insulating layer made of polyimide resin provided covering the conductor layer, the first layer provided on the insulating substrate A hybrid integrated circuit characterized by having a bonding pad provided on a conductor layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988096284U JPH0217839U (en) | 1988-07-19 | 1988-07-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988096284U JPH0217839U (en) | 1988-07-19 | 1988-07-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0217839U true JPH0217839U (en) | 1990-02-06 |
Family
ID=31321152
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988096284U Pending JPH0217839U (en) | 1988-07-19 | 1988-07-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0217839U (en) |
-
1988
- 1988-07-19 JP JP1988096284U patent/JPH0217839U/ja active Pending